COEN 6741 Grading Scheme ► Test#1: 30% ► Test#2: 30% ► Project: 40%
COEN 6741 Grading Scheme ► Test#1: 30% ► Test#2: 30% ► Project: 40%
COEN 6741: Project Grading Scheme ► Project (40%) 60% Project Report 20% Project Presentation (Posters) 10% Participation (Peer Evaluation Form) 10% Project Demo (TA’s Evaluation)
COEN 6741: Project Grading Scheme ► Project (40%) 60% Project Report 20% Project Presentation (Posters) 10% Participation (Peer Evaluation Form) 10% Project Demo (TA’s Evaluation)
COEN 6741: Project Report max. 20 pages (w/o code) 1) 1) Introduction 2) 2) Instruction Set Architecture Design and Encoding 3) 3) Datapath Design 4) 4) Control Unit Design 5) 5) Simulation and Testing Results 6) 6) Conclusions Handling Hazards
COEN 6741: Project Grading Scheme ► Project (40%) 60% Project Report 20% Project Presentation (Posters) 10% Participation (Peer Evaluation Form) 10% Project Demo (TA’s Evaluation)
COEN 6741: Project Presentation Poster incl. Q&A 1) 1) Objective 2) 2) Instruction Set Architecture Design and Encoding 3) 3) Datapath Design 4) 4) Control Unit Design 5) 5) Simulation and Testing Results 6) 6) Conclusions 7) 7) Poster Quality 8) 8) Answering Questions Handling Hazards
COEN 6741: Project Grading Scheme ► Project (40%) 60% Project Report 20% Project Presentation (Posters) 10% Participation (Peer Evaluation Form) 10% Project Demo (TA’s Evaluation)
COEN 6741: Project Grading Scheme ► Project (40%) 60% Project Report 20% Project Presentation (Posters) 10% Participation (Peer Evaluation Form) 10% Project Demo (TA) 0% Confirmation of Originality (mandatory!)
COEN 6741: Project Deadlines ► Project Reports: Wednesday April 6, before 5pm! Dr. Tahar’s Mailbox in EV-05 ► Project Posters: Thursday April 11.45am! Classroom: FG-B070 ► Project Demos: Friday April 8, time/place TBD!
COEN 6741: Test #2 ► Test#2: Thursday, March 11.45am Classroom: Classroom: FG-B070 Last Office Hours ► Monday, March 1:30-2:30pm Topics …
COEN 6741: Test#2 Topics ► Instruction-Level Parallelism: Loop Unrolling Dynamic scheduling (Tumasulo) Dynamic Branch Prediction (BHB, BTB) Multiple Issue (Superscalar, VLIW, Vector) ► Memory Hierarchy Design Memory Hierarchy (Organization, Access Time) Cache (Organization) Virtual Memory (TLB) ► Material allowed: Only Calculators (closed book!)
Good Luck Good Luck
COEN 6741: Another Last Remark
► Do you know how much real time, resources and CPU time is used for Verification vs. Design?
COEN 6741: Another Last Remark ► Do you know how much real time, resources and CPU time is used for Verification vs. Design? ► 70%!
COEN 6741: Another Last Remark ► Do you know how much time, resources and CPU time is used for Verification vs. Design? ► 70%! ► COEN6541: Functional Hardware Verification by Dr. O. Ait-Mohamed ► COEN6551: Formal Hardware Verification by Dr. S. Tahar
COEN 6741: Really Last Remark
► Teaching Evaluation Questionnaire
COEN 6741: Really Last Remark! ► Teaching Evaluation Questionnaire: Don’t forget to do it >!
COEN 6741: Really Last Remark! ► Teaching Evaluation Questionnaire: Don’t forget to do it on-line ASAP! … and now it’s time to go home! … and now it’s time to go home! Thank you & Good Luck Thank you & Good Luck