BITS Pilani Pilani Campus Pawan Sharma Lecture / ES C263 INSTR/CS/EEE F241 Microprocessor Programming and Interfacing

BITS Pilani, Pilani Campus  Disk Organization  Interpretation of Boot sector  File Allocation Table  Root Directory  Example Last Lecture

BITS Pilani, Pilani Campus  8086 architecture  Programmers Model Today’s Lecture

BITS Pilani, Pilani Campus 8086 Architecture

BITS Pilani, Pilani Campus 8086 Data Bus Control signals Add Bus A 0 A 19 D 0 D 15

BITS Pilani, Pilani Campus Memory Address Space A 19 ……………A 0 0……………… H 1……………….1 FFFFF H Memory Address Space H FFFFF H

BITS Pilani, Pilani Campus  Allows the microprocessor to address only the first 1MB of memory space, even if it is Core2 or i5 or i7 microprocessor.  First 1MB of memory is called the DOS memory system. DOS requires the CPU to work in real mode.  Real mode is characterized by a 20 bit segmented memory address space (giving exactly 1 MB of addressable memory) and unlimited direct software access to all memory (no protection), I/O addresses and peripheral hardware. Real Mode Memory Addressing

BITS Pilani, Pilani Campus BIU ALU Control & Timing EU Address bus RAMROM I/o Ports Discs Video Data Bus CLK System Block Diagram

BITS Pilani, Pilani Campus  BIU (Bus Interface Unit)  provides hardware functions for generation of the memory and I/O addresses for the transfer of data between itself and the outside world  (Queue, segment registers & IP)  EU (Execution Unit)  receives program instruction codes and data from the BIU, executes these instructions and stores the results in the general- purpose registers  (Control ckt, Instruction decoder, ALU, GP registers, SP,SI,DI,BP) CPU Components

BITS Pilani, Pilani Campus IP 16bit CS DS ES SS Code Segment register Data Segment register Extra Segment register Stack Segment register Instruction Pointer Programmers Model : CPU H/W which is Program visible: referenced directly during application programming CPU H/W which is Program invisible: can not be referenced directly by programmer but internally involved

BITS Pilani, Pilani Campus  Laundry Example  Four persons each have one load of clothes to wash, dry, and fold  Washer takes 30 minutes  Dryer takes 40 minutes  “Folder” takes 20 minutes Pipelining: Its Natural! ABCD

BITS Pilani, Pilani Campus Sequential Laundry ABCD PM Midnight TaskOrderTaskOrder Time

BITS Pilani, Pilani Campus Pipelined Laundry :Start work ASAP ABCD 6 PM Midnight TaskOrderTaskOrder Time Pipelined laundry takes 3.5 hours for 4 loads

BITS Pilani, Pilani Campus Key Definitions  Pipelining is a key implementation technique used to build fast processors. It allows the execution of multiple instructions to overlap in time.  The throughput of an instruction pipeline is the measure of how often an instruction exits the pipeline.

BITS Pilani, Pilani Campus  Pipelining doesn’t help latency of single task, it helps throughput of entire workload  Pipeline rate limited by slowest pipeline stage  Multiple tasks operating simultaneously  Potential speedup = Number pipe stages  Unbalanced lengths of pipe stages reduces speedup  Time to “fill” pipeline and time to “drain” it reduces speedup Pipelining Lessons ABCD 6 PM 789 TaskOrderTaskOrder Time

BITS Pilani, Pilani Campus  BIU stores pre-fetched bytes (six instruction bytes for the following instructions) in a FIFO register called the queue register.  Helps CPU execute instructions much faster  In case of JMP or CALL instructions, the queue needs to be dumped.  Fetching the next instruction while the current instruction executes is called pipelining. Queue Register

BITS Pilani, Pilani Campus IP = 3000 H CS = 2000 H Base address Offset address Physical address = H H H 2000 H : 3000 H Segment-Offset Addressing Scheme

BITS Pilani, Pilani Campus Example Segment Addresses Segment Register Starting AddressEnding Addresses 2000 H 2001 H 2100 H AB00 H 1234 H H H H AB000 H H 2FFFF H 3000F H 30FFF H BAFFF H 2233F H

BITS Pilani, Pilani Campus Data Code Stack Extra 4900 ES 3400 SS 1000DS 2000 SS H H H 1FFFF H 2FFFF H H 43FFF H H 58FFF H Memory Segmentation

BITS Pilani, Pilani Campus AX BX CX DX SP BP SI DI Count Data Stack Pointer Base Pointer Source Index Destination Index Programmers Model (EU): Accumulator Base Index

BITS Pilani, Pilani Campus AX AH (8 bit) AL (8 bit) BX BHBL CX CHCL DX DHDL (Accumulator) (Base Register) (Used as a counter) (Used to point to data in I/O operations)

BITS Pilani, Pilani Campus MULTIPURPOSE REGISTERS AX, BX, CX, DX, BP, DI, SI SPECIAL PURPOSE REGISTERS IP, SP, FLAGS CS, DS, SS, ES ( Segment Registers )

BITS Pilani, Pilani Campus 8086 – Default 16 bit segment and offset address combinations Segment offset special purpose CS SS DS ES IP SP (or) BP BX,DI,SI an 8-bit number 16 – bit number DI for string Instructions Instruction Address Stack address Data address String destination address

BITS Pilani, Pilani Campus EAX AX EBX BX ECX CX EDX DX ESP SP EBP BP 32-bit registers in through Core2

BITS Pilani, Pilani Campus ESI SI EDI DI EIP IP EFLAGS Flags

BITS Pilani, Pilani Campus  A flag is a flip flop that indicates some condition produced by the execution of an instruction or controls certain operations of the execution unit.  A 16-bit flag register in the EU contains nine active flags.  Conditional Flags /Status Flags  C (Carry)  P (Parity)  Z (Zero)  S (Sign)  A (Auxiliary Carry)  O (Overflow)  Control Flags  I (Interrupt)  D (Direction)  T (Trace) Flags

BITS Pilani, Pilani Campus ODITSZAPC (8088/186/188) bits bits bits Pentium/ Pentium IV 21 bits

BITS Pilani, Pilani Campus ES CS SS DS IP  Control & Timing Memory Interface ALU Operands Flags AHAL BHBL SP BP SI DI CHCL DHDL EU BIU Instruction Queue Block Diagram of 8086