Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The block diagram of the CMOS readout circuit structure. Figure Legend: From: Design.

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Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The block diagram of the CMOS readout circuit structure. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The readout circuit structure of each pixel. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The gain curve versus frequency of the transfer function for the CDS circuit. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The clock timing waveforms of the main driving signals and the output. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Micrograph of part of the 64×64-element readout chip. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Block diagram of the testing bench. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The typical output voltage signal of the readout chip. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The root mean square voltage and power spectrum of the output noise of the readout chip. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Output voltage versus photogenerated current. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /

Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Output voltage versus integration time. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10): doi: /