Implementation of Real Time Image Processing System with FPGA and DSP Presented by M V Ganeswara Rao Co- author Dr. P Rajesh Kumar Co- author Dr. A Mallikarjuna Prasad IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMPUTING AND COMMUNICATION (MICROCOM 2016)

Contents Introduction Hardware Architecture Working Of Image Processing System FPGA functions Edge Detection System Framework Experimental Results Conclusions References

Introduction In recent years, image processing is playing key role in finding solution to many problems in fields such as medical, industry, security, remote sensing applications and so on. But in some applications system performance has become bottle neck. Most of the image processing systems are developed based on Desktop PC which is more generic for image processing applications and these systems may not meet the requirement of real time performance

Along with the development of advanced and computationally intensive image processing algorithms, computational platforms based on FPGA chip and DSP processor are also developed This paper presents an image processing system based on an FPGA chip and DSP processor. In this system the TMS320DM642 DSP is used as image processing core and a Xilinx FPGA chip is used for image sampling and display.

Hardware Architecture

Working Of Image Processing System 1.A image frame is acquired from the CCD camera, and then the captured image frame data which is in YUV 4:2:2 format is converted to YUV 4:2:0 format. 2.The frame is fed to the video decoder. This decodes the image frame and outputs the decoded image data. 3.The decoded image data is stored in SDRAM 4.The TMS320DM642 DSP reads image data from the SDRAM and then it runs image processing algorithm on them. 5.Processed image data is fed to the video encoder 6.The encoder can drive out RGB, HD component video, NTSC/PAL composite video, or S-video. 7.The frame is then displayed on the output device (SDTV).

YYYYUVYYYYUVY……… … ---One pixel data-- -- YUV 4:2:0 data order in SDRAM

FPGA Functions In this system FPGA is used as a control unit for image sampling and display. The EMIF is used as a communication interface between FPGA, DSP, SDRAM and flash memory The DSP processor enables CE0, CE1, and CE2 and CE3 which are routed to the daughter card interface connectors Chip SelectFunction CE0SDRAM bus CE18 bit Flash, UART, FPGA functions CE2Daughter Card Interface CE3 FPGA Sync Registers Daughter Card Interface

Edge Detection Sobel 3X3 Edge detection masks

System Framework

Experimental Results

Conclusions The proposed system successfully executed the algorithm and edge detected video frames are displayed on PAL display monitor. It is tested on various video frames and also with different lighting conditions. Under those conditions also this system successfully displayed the video frames on monitor without any lag. It is also observed that the proposed system has large flexibility to implement different computationally intensive image processing algorithms.

References 1.H.X. Zhou, R. Lai, S.Q. Liu. A New Real Time Processing System for Imaging Signal Based on DSP & FPGA [J]. Infrared Physics & technology. 2005,46(4): J. Batlle, J. Marti, P. Ridao. A New FPGA/DSP-Based Parallel Architecture for Real-time Image Processing [J]. Real-Time Imaging, 2002,8(5): M. Jyothi Poorna, M.V. Ganeswara Rao, P.Rajesh Kumar and A.Mallikarjuna Prasad. FPGA Implementation of Skin Tone Detection Accelerator for Face Detection. Advance in Electronic and Electric Engineering. ISSN , Volume 3, Number 9 (2013), pp C.Qi, Y.H. Chen, T.S. Huang. The Real-time Image Processing Technique Based on DSP[J]. Wuhan University Journal of Natural Sciences, 2005,10(6): TMS320DM642Evaluation Module Technical Reference Digital spectrum incorporated, Rev. A August 2003.