Peter Jansweijer Nikhef Amsterdam Electronics- Technology November 21, 2012KM3NeT, CLBv2 Meeting via EVO KM3NeT CLBv2 1.

Slides:



Advertisements
Similar presentations
April 30, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
Advertisements

EES: Burn – in test Eliminate infant mortality: Not possible to detect it with AOI, FPT, X-ray or ICT! 1.
June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
October 8, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
1 Design of the Front End Readout Board for TORCH Detector 10, June 2010.
Paolo Musico on behalf of KM3NeT collaboration The Central Logic Board for the KM3NeT detector: design and production Abstract The KM3NeT deep sea neutrino.
Marseille 30 January 2013 David Calvo IFIC (CSIC – Universidad de Valencia) CLB: Current status and development on CLBv2 in Valencia.
Input/OUTPUT [I/O Module structure].
P. Jansweijer Nikhef Amsterdam Electronics- Technology October 15, 20091VLVnT-09 Athens Measuring propagation delay over a coded serial communication channel.
SODA: Synchronization Of Data Acquisition I.Konorov  Requirements  Architecture  System components  Performance  Conclusions and outlook PANDA FE-DAQ.
February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
August 06, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
NS Training Hardware.
July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.
ECE 526 – Network Processing Systems Design Computer Architecture: traditional network processing systems implementation Chapter 4: D. E. Comer.
May 29, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
September 11-12, 2013KM3NeT, CLBv2 Workshop Valencia Peter Jansweijer Nikhef Amsterdam Electronics- Technology Shore station brainstorm 1.
December 04, 2013KM3NeT, CLBv2 Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
January 28, 2015CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
GBT SCA overview Slide 1-5 Work status Slide 6-10 Shuaib Ahmad Khan.
August 22, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
July, IFIC (CSIC – Universidad de Valencia) CLB: MULTIBOOT 1.
January 28-30, 2014KM3NeT, Electronics Workshop A‘dam Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
Firmware Overview and Status Erno DAVID Wigner Research Center for Physics (HU) 26 January, 2016.
NIKHEF 2014 David Calvo IFIC (CSIC – Universidad de Valencia) Time to Digital Converters for KM3NeT Data Readout System.
December 10, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
S.Anvar, V.Gautard, H.Le Provost, F.Louis, K.Menager, Y.Moudden, B.Vallage, E.Zonca, on behalf of the KM3NeT consortium 1 IRFU/SEDI-CEA Saclay F
VC707 Evaluation Kit Xilinx Virtex-7 In_0 GTX MHz IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B IDELAYCTRL LHC_Clk.
Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 14, 2012KM3NeT, CLBv2 Meeting via EVO KM3NeT CLBv2 1.
29 Oct, 2014 IFIC (CSIC – Universidad de Valencia) CLB: Current status and development.
November 2014, Groningen/Dwingeloo, the Netherlands 3rd International VLBI Technology Workshop Peter Jansweijer Nikhef Amsterdam Electronics- Technology.
LM32 DEVELOPMENTS ONGOING WORK ON TDCs AND OTHER ISSUES (LM32) Diego Real David Calvo CLB group online meeting, 27 March
H.Z. Peek Nikhef Amsterdam Electronics- Technology KM3NeT General Assembly Meeting Catania, 20-23, February White Rabbit Sub-Nanosecond timing over.
Genova May 2013 Diego Real – David Calvo IFIC (CSIC – Universidad de Valencia) CLBv2 1.
J-W Schmelling Nikhef Amsterdam Electronics- Technology of January PPM-DU optics for KM3NeT Collaboration meeting Marseille PPM-DU: A three.
March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
System On Chip Offshore Node S. Anvar, H. Le Provost, Y.Moudden, F. Louis, B.Vallage, E.Zonca – CEA Saclay IRFU – Amsterdam/NIKHEF, 2010 July 5.
3 Dec, 2013 IFIC (CSIC – Universidad de Valencia) CLB: Current status and development.
Electronics Department Amsterdam 5-July-2010 Sander Mos 1 Status and progress of NIK* Logic WPFL - 5 July 2010 Amsterdam * Network Interface Kit.
DOM Electronics (Digital Optical Module) 1 WPFLElectronics PPMDOM ElectronicsF. Louis.
Firmware and Software for the PPM DU S. Anvar, H. Le Provost, Y.Moudden, F. Louis, E.Zonca – CEA Saclay IRFU – Amsterdam/NIKHEF, 2011 March 30.
May 8, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
Peter Jansweijer Nikhef Amsterdam Electronics- Technology September 19, 2012KM3NeT, CLB/DAQ Videocon KM3NeT CLBv2 1.
July 31, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
Grzegorz Kasprowicz1 Level 1 trigger sorter implemented in hardware.
DHH progress report Igor Konorov TUM, Physics Department, E18 DEPFET workshop, Bonn February 7-9, 2011 Outline:  Implementation synchronous clock distribution.
October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
CLB demonstration board & prototype tests (CLB: Central Logic Board) 1 WPFLElectronics PPMCLB F. Louis.
KM3NeT status Neutrino telescope in the Mediterranean Sea Dorothea Samtleben, NIKHEF Jamboree December 2012.
April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
September 11-12, 2013KM3NeT, CLBv2 Workshop Valencia Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.
P. Jansweijer Nikhef Amsterdam Electronics- Technology Amsterdam July 5-6, 2010KM3NeT: General WPF/L meeting 1 Measuring time offset over a bidirectional.
Off & On Shore Electronics overview KM3Net APC Paris 05 / 09 / 2012 Frédéric LOUIS.
White Rabbit and KM3NeT Peter Jansweijer, on behalf of KM3NeT
The Data Handling Hybrid
Diego Real, IFIC Spain, KM3NeT Electronics Coordinator
Status on development of a White Rabbit Core
WR & KM3NeT Peter Jansweijer
Data and Control link via GbE
“FPGA shore station demonstrator for KM3NeT”
CLB: Current status and development
KM3NeT CLBv2.
KM3NeT CLBv2.
KM3NeT CLBv2.
Kostas Manolopoulos Tasos Belias
KM3NeT CLBv2.
MULTIBOOT AND SPI FLASH MEMORY
Commodity Flash ADC-FPGA Based Electronics for an
Presentation transcript:

Peter Jansweijer Nikhef Amsterdam Electronics- Technology November 21, 2012KM3NeT, CLBv2 Meeting via EVO KM3NeT CLBv2 1

Peter Jansweijer Nikhef Amsterdam Electronics- Technology November 21, 2012KM3NeT, CLBv2 Meeting via EVO Ethernet based Current implementation “DOM in Antares” Switch DOM SFP Buffer SFP Broadcast Optical Network Timing Start Rx Tx Stop1  : DDMTD Reference Clock Stop2 Stop3 Stop4 MAC does not tolerate discontinuities in transmission Timing calibration corrupts Ethernet Packets (=> need TCP/IP) Shore Station interface 2 Rx  : DDMTD Rx  : DDMTD Rx  : DDMTD Note: Current implementation supports one DOM only! (broadcast not yet implemented!) Errata!

Peter Jansweijer Nikhef Amsterdam Electronics- Technology November 21, 2012KM3NeT, CLBv2 Meeting via EVO Ethernet based Current implementation “DOM in Antares” MAC does not tolerate discontinuities in Ethernet frames on its input The “gap” that results from a removed timing marker (e.g. “command”; 2 clock ticks) causes the MAC to generate “bad frame” The gap is avoided by switching to a 2 clock tick shorter pipeline whenever a timing marker is recognized 3 MAC good_frame bad_frame = Timing Marker? Preamble D555 SFDTiming MarkerdataFCS ## 2. Data Link data “Frame” Preamble D555 SFDFCS ## 2. Data Link data The MAC is happy!

Peter Jansweijer Nikhef Amsterdam Electronics- Technology November 21, 2012KM3NeT, CLBv2 Meeting via EVO Further status: LM32 ◦ Synthesis via XST running ◦ GDB via JTAG (Xilinx versus Lattice) needs study ◦ Place White Rabbit: Wishbone crossbar, UART DPRAM in place… Ongoing. Soft-PLL FMC card schematics ready to be checked. 4

Peter Jansweijer Nikhef Amsterdam Electronics- Technology November 21, 2012KM3NeT, CLBv2 Meeting via EVO 5 Central Logic Board (CLB) Rx_mac2buf 2 nd CPU LM32 MEM I2CUART Fifo 31 TDCs TDC 0 Management & Control Data Control Wishbone shared bus (32 bits) RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone State Machine Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 TempCompassTilt Point to Point interconnection Xilinx Kintex-7