RADWG Meeting April 2015 Salvatore Danzeca EN/STI/ECE

AGENDA What’s new by Salvatore Danzeca Workshop on a harmonized mixed-signal flow by Gilles Foucard Cryo tests at CHARM by Nikolaos Trikoupis, Juan Casas-Cubillos CHARM Update by Julien Mekki Co60 Gamma Facility update by Adam Thornton

What’s new – What’s next PSI Facility Updates We restarted the components test last week ADC: ADS7852Y 8-channel, 12-bit 500KSps Latchup sensitive SRAM memories LatMon Test dateComponentsTest groupEquipment owner AprilADC – Memories SEL - LatMonEN/STI TE/EPCTE/EPC 9-10 MaySRAM memories SEU – CELESTA?EN/STI JuneFPGA – SMARTFUSION 2 – Photo Mos? QPS TE-MPE JulyADC? bits? Aug? 5-6 Sep?

FPGA It is needed in most of the equipment New solutions for HL to be found now Good news: ProAsic3 will be still produced for the next 10 years. (From the Microsemi workshop at CERN) Bad News Still the limitation on reprogrammability as function of the dose Few hundreds of Gy (400) of TID lifetime NEW SOLUTION: IGLOO2-SMARTFUSION2 WAITING FOR RAD-HARD development from ST and ESA

FPGA – SMARTFUSION2- IGLOO2 First silicon : Found to be sensitive to Latches/microlatches New silicon ( ): Not sensitive to Latches (to be tested) Plan: 1 FPGA procurement 2 Carried Board procurement 3 Test planning 4 Radiation Test DONE X10 SmartFusion2 NEW SILICON YOUR INPUT IS NEEDED TO NOT REPEAT THE TESTS 1)Custom Board 2)Dev KIT TO BE SCHEDULED

Communication link WorldFIP dead end, new HL-LHC requirements in terms of performance and radiation hardness (TE-EPC, QPS, ?) GBTx + ProAsic3 (GEFE BE/BI, MOPOS BE/BI) GBTx + SSDP (ESA + BE/CO + TE/EPC as test case) ETHERCAT: Ethernet Fieldbus. The good is that no cabling is needed GBTx solutions would be adaptable in a fieldbus like link? ETHERCAT can be really implemented?

ADC bits A common development is needed and strongly suggested for a rad-hard ADC. ATMEL.. Others? Specifications: 18 bit <1MSPs 24 bit <500 KSPs NO Solution up to know but we NEED to find it