Design of the 64-channel ASIC: update DEI - Politecnico di Bari and INFN - Sezione di Bari Meeting INSIDE, December 18, 2014, Roma Outline  Proposed solution for the 10-bit ADC  Status of the design  Planning and schedule

A/D conversion: open issue (from the previous meeting) 2  Dithering, oversampling (with a factor 16) and decimation proposed to increase the resolution of the available 8-bit ADC to 10 bits - If the conversion rate of the 8-bit ADC is 20MHz (rather optimistic) we need about T conv =1  s for the conversion of one channel - If we have only one channel to be converted per event and the event rate is 16kHz, roughly, the probability of losing an event is 2% - If the event rate is increased of an order of magnitude, this probability becomes about 15%  This solution becomes unacceptable in case we have an appreciable probability that more than one channel of the ASIC is over threshold for each event. For instance, the conversion of 64 channels would take 64  s, thus, in this case, we would have a conversion rate of about 15kHz/ASIC (which would worsen if the 8-bit ADC max conversion rate is less than 20MHz)  According to the discussion in Turin, a conversion rate of at least about 30kHz/ASIC (full 64 channels converted) is needed  Multiple ADC operated in parallel in order to generate more samples at the same time can be a solution, but this entails more power consumption and problems of effective management of the ADC resources available among the channels (complex routing and switching)  Alternative solutions must be found Meeting INSIDE, December 18, 2014, Roma

Proposed solution: pipeline ADC 3 Meeting INSIDE, December 18, 2014, Roma  It is possible to exploit very simple 1-bit ADC stages in a pipeline structure to increase the resolution of our 8-bit ADC  Only two 1-bit ADC stages in front of the 8-bit ADC are needed to increase the resolution to 10 bits

Adding redundancy: 1.5-bit ADC 4 Meeting INSIDE, December 18, 2014, Roma  To avoid problems due to offset of the comparator used in the 1-bit structure, we add redundancy V in < -V REF /8  b 1 =0 b 0 =0 -V REF /8 < V in < +V REF /8  b 1 =0 b 0 =1 V in > +V REF /8  b 1 =1 b 0 =1  The residue is now: V RES = V in -(b 0 +b 1 -1)V REF /4  V OUT = 2V RES is the output of the 1.5-bit stage  Three possible cases:  In other words we have a three-level quantization, so this stage gives more information than a 1-bit ADC, but less than a 2-bit ADC  Two stages in front of our 8-bit ADC provide 4 bits, which are reduced to 2 bits by a very simple digital decoding circuit

Circuit implementation of the 1.5-bit ADC 5 Meeting INSIDE, December 18, 2014, Roma  Very simple: two comparators, a three input MUX, some switches and the multiplying stage  Accurate value of the gain is mandatory: to obtain exactly a gain of 2, switched capacitor structures are used  The redundancy introduced is able to compensate the comparator offsets  0 and  1 as long as their absolute values are less than V REF /4, making easier the design of the comparators.

Structure of the 10-bit ADC 6 Meeting INSIDE, December 18, 2014, Roma  Two 1.5-bit ADC stages, followed by a S&H circuit (needed for decoupling purposes) and the 8-bit ADC  Timing and phase management

Rate of conversion 7 Meeting INSIDE, December 18, 2014, Roma  The first conversion takes: T conv = T CK (1 st 1.5-bit ADC) + T CK /2 (2 nd 1.5-bit ADC) + T CK /2 (S&H phase) + 2T CK (AutoZero, Coarse Conversion, Fine Conversion, Correction phases of the 8-bit ADC) = 4T CK  If the max clock frequency is 5MHz (rather conservative), T CK =200ns, thus the first conversion takes 800ns  Thanks to the pipelined structure, the conversion of the other channels take only 1 clock cycle per channel  In case we must read-out and convert all the 64 channels, this would take 800ns+63*200ns=13.4  s, which corresponds roughly to 75kHz/ASIC, reasonably more than required.

 ADC design finished at layout level: post-layout final verifications to be completed Status of the design 8 BlockCircuit level Layout level Analog channelxx ‘Fast’ and ‘slow’ comparatorsxx Peak detectorxx DACs and bias circuitsxx ADC interface amplifierxx LVDS buffers and receiversxx Digital part*xx  All the analog blocks have been defined at layout level (ADC interface amplifier included)  The final layout of the digital part has not been generated yet Meeting INSIDE, December 18, 2014, Roma

Planning and schedule 9  To be done: - Flooplan, placement and routing of the blocks - According to the floorplan, generation of the final layout of the digital part - Assembly of the ASIC - Realistic estimation: at least 2 months of work needed  Manpower problems  Next available MPW run deadline: February 2nd, unlikely to be met  Submission expected for the next MPW deadline (April 7th) Meeting INSIDE, December 18, 2014, Roma