PXD EVO November 18, 2014 ASIC Review 1 H-.G. Moser, 18 th B2GM, June 2014 Date and Location MPP, October 27, 10:00 – October 28, 16:00, Room 313 Reviewers: Gary Varner (Hawaii) Wladislaw Dabrowski (AGH Krakau) Valerio Re (Uni Bergamo, INFN Pavia)

PXD EVO November 18, 2014 Sensor and ASICs 2 Switcher Control of gate and clear 32 x 2 channels Switches up to 30V AMS 0.18 µm HV technology DCDB Amplification and digitization of DEPFET signals 256 input channels 8-bit ADC per channel 92 ns sampling time UMC 180 nm DHP Signal processor Common mode correction Pedestal subtraction 0-supression Timing and trigger control TSMC 65nm (first version IBM 90nm) DEPFET sensor 250 x 768 pixel 50µm x 55µm (min) 50µm x 80µm (max) 75µm thick

PXD EVO November 18, 2014 Charge 3 The review should assess the production readiness of the three ASICs used in the Belle II PXD. The schedule requires a submission of the final AISCs early In order to achieve this one has to assess: The maturity of the chip design. Completeness and quality of documentation. Status of performance tests (stand alone and on system level). Known problems and mitigation/correction plans. Missing measurements and tests. Work plan (responsibilities, milestones). Schedule for next submission. QA strategy. It is likely that the review will conclude that there are still some issues to be resolved before a submission can be done. In this case the risks for the detector performance need to be evaluated. A clear strategy should be developed how to achieve the goal of timely submission. Following issues need to be discussed: General introduction in the chip design and specifications Summary of tests and performance information Design changes planned for the next submission Information on QA strategy (information on yield expectations, test programs, status of test equipment, its documentation)

PXD EVO November 18, 2014 Schedule 4 Assemble Pilot Run modules with existing ASICs: April 2015 ASIC submission in June 2015 Series module assembly to start in November 201 ASIC submission date close to end of the present funding period! Copper processing of main batches can start after test! Overall scheduleAll sensors produced and tested till February 2016 Module/Ladder assembly starts in November 2015 All ladders produced till May 2016 PXD shipment to KEK in August Months contingency (assuming Phase II starts in December 2016 )

PXD EVO November 18, 2014 Switcher 5 General comments: Generally in good shape: Concept proven Performance: only concern is speed of Clear signal Required changes look modest Concern regarding radiation hardness of the HV transistors We endorse performing detailed tests of the Gated Mode operation

PXD EVO November 18, 2014 Switcher (specific comments) 6 The maturity of the chip design: Quite mature. Completeness and quality of documentation: Comprehensive Specification document lacking. Reference Manual is a good start, needs to be expanded to include performance requirements. Status of performance tests: Additional Gated Mode testing needed. Further radiation hardness testing likewise needed. Known problems and mitigation/correction plans: Main issue understood and plausible corrective plan proposed. Needs to be implemented. Missing measurements and tests: Addressed above. Work plan (responsibilities, milestones): Recommend clarifying test program leading to ASIC revision. Designer needs to clarify scope of modification, which will drive the schedule. Schedule for next submissions: June submission plausible, if consistent with above estimates. QA strategy: General test plan looks reasonable. The committee expresses concern regarding the proposed ASIC modifications to support multiplexed testing (additional HV-LV conversion, output multiplexing).

PXD EVO November 18, 2014 Switcher 7 Recommendations: End users should review Reference Manual for completeness Are pin table listings sufficient? Interface control description adequate? Recommend creating Hardware Description Language description of Gating functional Concern regarding radiation hardness of the HV transistors: We endorse performing detailed tests of the Gated Mode operation We recommend investigating long-term burn-in/stress testing of HV operation Actions: ‘end users’ to send comments to Christian Kreidl (?) till end of the year? Ivan to provide hardware description language Irradiations: Karlsruhe? Mannheim? When? Tests of gated mode with hybrid 4 and EMCM started (Eduard Prinker). Conclusive tests need PXD9 modules (April). Who can setup a long term test?

PXD EVO November 18, 2014 DCD 8 General comments: Basic architecture looks well suited to the requirements The committee expresses serious concerns about the details of the ADC implementation Unclear if problems observed are sensitivities to process parameters Further design work needed

PXD EVO November 18, 2014 DCD (specific comments) 9 The maturity of the chip design. We foresee significant additional design effort to address concerns regarding the ADC implementation Completeness and quality of documentation: A comprehensive Specification Document is lacking. Reference Manual is a good start, needs to be expanded to include performance requirements. Status of performance tests: Strongly recommend further testing to understand variety of pathologies observed. Further ASIC/channel testing statistics are needed. Known problems and mitigation/correction plans: Matching of observation with simulation is mandatory. Missing measurements and tests: More an issue of understanding results observed that missing measurements. Encourage further, cross-checked analyses. Work plan: Highly important that before next submission these problems are fully understood, to avoid excessive risk in resubmission. Schedule for next submissions: Given the above concerns, a February submission seems very aggressive. Items above must be resolved prior to submission. Verifying Monte Carlo spreads will likely take time, and sufficient time should be allocated. QA strategy: Generally looks OK.

PXD EVO November 18, 2014 DCD 10 Recommendations: Better understanding of noise performance and instabilities needed Consider an SEU test of the DCD More work is needed prior to a next submission. Submission schedule should be driven by the readiness to address the above issues. Careful consideration should be given to assess risk versus rewards of the changes proposed. Actions: Update documentation: Ivan? More measurements (on hybrid, EMCM): who can contribute? Simulations: Ivan? Irradiation tests (incl. SEU): together with Switcher?

PXD EVO November 18, 2014 DHPT 11 General comments: Specifications still not concisely presented Overall architecture looks very sound Cannot put all effort on the ASIC side. System engineering of cabling and interconnects, and an agreed-upon model for output load is needed. Complexity makes testing difficult

PXD EVO November 18, 2014 DHPT (specific items) 12 The maturity of the chip design: Data flow, PLL, synthesized logic are very mature. Remaining concern is in the verification of the high- speed interfaces. Completeness and quality of documentation: Specifications for output loads and timing are needed for signals in Table 1 of the Manual. For such a complex device, a more comprehensive document many be required. Status of performance tests (stand alone and on system level): Most IP Block / Task items test results well documented. Remaining issues well presented. Known problems and mitigation/correction plans: Proposed further testing seems adequate. Missing measurements and tests: Finer step TID testing, SEU testing. Channel masking and Overflow handling tests self-identified. Work plan: Not clear who is doing what to provide further testing and by when. A detailed model of the cabling needed to complete output driver redesign. Schedule for next submissions: June submission seems plausible given proposed testing schedule. A rigorous internal review of the proposed changes should be held prior to release for submission. QA strategy: Proposed quality control plan seems adequate.

PXD EVO November 18, 2014 DHPT 13 Recommendations: Characterize the electrical properties of the external interconnects and cables Actions: Complete documentation. Complete performance tests (hybrid, EMCM, PXD9). Characterization (and measurement) of external interconnects. Further measurements and optimization of external links. TID and SEU tests (take into account spectrum of neutrons ).

PXD EVO November 18, 2014 Summary 14 Documentation needed for all ASICs Design issues: DCD: simulations of ADC performance needed Measurements: more setups/manpower needed DCD: more statistics DHPT: communication with DCD/switcher: gated mode sequences Support: characterization of data links Irradiation tests (incl. SEU)