1 Progress report on the LPSC-Grenoble contribution in micro- electronics (ADC + DAC) J-Y. Hostachy, J. Bouvier, D. Dzahini, L. Galin-Martel, E. Lagorio,

Slides:

Advertisements

Similar presentations

HIPPO, a Flexible Front-End Signal Processor for High-Speed Image Sensor Readout Carl Grace, Dario Gnani, Jean-Pierre Walder, and Bob Zheng June 10, 2011.

Advertisements

Calice Meeting – Prague September 12 th Design of a 16 bit  DAC for ECAL calibration Status report D. Dzahini, L. Gallin-Martel, O. Rossetto,

MB Page1Mihai Banu, July 2002 WCR #7 Nyquist rate ADC Main design motivation: Low Power Features: Pipeline arquitecture. Two interleaved ADCs with shared.

R&D for ECAL VFE technology prototype -Gerard Bohner -Jacques Lecoq -Samuel Manen LPC Clermond-Ferrand, Fr -Christophe de La Taille -Julien Fleury -Gisèle.

EE435 Final Project: 9-Bit SAR ADC

SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.

Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State.

18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.

7 th International Meeting on Front-End Electronics, Montauk NY – May 18 th - 21 st, 2009 Cyclic-ADC developments for Si calorimeter of ILC Laurent ROYER,

SiLC Front-End Electronics LPNHE Paris March 15 th 2004.

Ph. Farthouat CERN ELEC 2002 ADC 1 Analog to Digital Conversion  Introduction  Main characteristics –Resolution –Dynamic range –Bandwidth –Conversion.

PH4705/ET4305: A/D: Analogue to Digital Conversion Typical Devices: Data sheets are on the web site for A/D 8 bit parallel AD7819 and serial ADC0831 And.

L. Gallin-Martel, D. Dzahini, F. Rarbi, O. Rossetto

By Grégory Brillant Background calibration techniques for multistage pipelined ADCs with digital redundancy.

L.Royer– Calice DESY – July 2010 Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand R&D LPC Clermont-Fd dedicated to the.

L.Royer– TWEPP – 22 Sept Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand Signal processing for High Granularity Calorimeter: Ampliﬁcation,

Second generation Front-end chip for H-Cal SiPM readout : SPIROC DESY Hamburg – le 13 février 2007 M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G.

S.Manen– IEEE Dresden – Oct A custom 12-bit cyclic ADC for the electromagnetic calorimeter of the International Linear Collider Samuel.

FE8113 ”High Speed Data Converters”. Part 3: High-Speed ADCs.

Front-End electronics for Future Linear Collider calorimeters C. de La Taille IN2P3/LAL Orsay on behalf of the CALICE and EUDET collaborations

New Power Saving Design Method for CMOS Flash ADC Institute of Computer, Communication and Control, Circuits and Systems, July 2004 IEEE 班級：積體碩一姓名：黃順和.

L.ROYER – TWEPP Oxford – Sept The chip Signal processing for High Granularity Calorimeter (Si-W ILC) L.Royer, J.Bonnard, S.Manen, X.Soumpholphakdy.

Why Data Conversion? Real world is analog Mostly, communication and computation is digital Need a component to convert analog signals to digital (ADC)

Technical Report High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and Engineering Department The Pennsylvania.

L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.

1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN.

L.Royer – Calice Manchester – Sept A 12-bit cyclic ADC dedicated to the VFE electronics of Si-W Ecal Laurent ROYER, Samuel MANEN LPC Clermont-Ferrand.

LC Power Distribution & Pulsing Workshop, May 2011 Super-ALTRO Demonstrator Test Results LC Power Distribution & Pulsing Workshop, May nd November.

Low Power, High-Throughput AD Converters

1 Quarterly Technical Report II for Pittsburgh Digital Greenhouse Kyusun Choi The Pennsylvania State University Computer Science and Engineering Department.

Low Power, High-Throughput AD Converters

SKIROC ADC measurements and cyclic ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting Orsay June.

1 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Development & System Level Considerations.

M. TWEPP071 MAPS read-out electronics for Vertex Detectors (ILC) A low power and low signal 4 bit 50 MS/s double sampling pipelined ADC M.

Front-End electronics for Future Linear Collider calorimeters C. de La Taille IN2P3/LAL Orsay On behalf of the CALICE collaboration

Aurore Savoy-Navarro 1), Albert Comerma 2), E. Deumens 3), Thanh Hung Pham 1), Rachid Sefri 1) 1) LPNHE-Université Pierre et Marie Curie/IN2P3-CNRS, Fr.

Technical Report 4 for Pittsburgh Digital Greenhouse High Speed CMOS A/D Converter Circuit for Radio Frequency Signal Kyusun Choi Computer Science and.

14 jan 2010 CALICE/EUDET FEE status C. de LA TAILLE.

1 Second generation Front-end chip for H-Cal SiPM readout : SPIROC Réunion EUDET France – LAL – jeudi 5 avril 2007 M. Bouchel, F. Dulucq, J. Fleury, C.

June 13rd, 2008 HARDROC2. June 13rd, 2008 European DHCAL meeting, NSM 2 HaRDROC1 architecture Variable gain (6bits) current preamps (50ohm input) One.

Design of the 64-channel ASIC: update DEI - Politecnico di Bari and INFN - Sezione di Bari Meeting INSIDE, December 18, 2014, Roma Outline  Proposed solution.

Sill Torres: Pipelined SAR Pipelined SAR with Comparator-Based Switch-Capacitor Residue Amplification Pedro Henrique Köhler Marra Pinto and Frank Sill.

Low Power, High-Throughput AD Converters

Electronics for Si-W calorimeter LCWS06 Bangalore – March, 10 th Gérard Bohner, Pascal Gay, Jacques Lecoq Samuel Manen, Laurent Royer Michel Bouchel, Bernard.

1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting London 2008.

A high speed 10 to 12 bits pipe line ADC, design proposal for ECAL

SKIROC status Calice meeting – Kobe – 10/05/2007.

SOCLE Meeting Dec Roman Pöschl LAL Orsay On behalf of the groups performing Electronics R&D - Introduction - SKIROC2 – Handling the large Dynamic.

CALICE ECAL meeting VFE ASIC Next & next to next version 17 Janvier 2006, LAL Orsay.

Spring 2006CSE 597A: Analog-Digital IC Design Scan-Flash ADC Low Power, High-Throughput AD Converters Melvin Eze Pennsylvania State University

A 12-bit low-power ADC for SKIROC

A General Purpose Charge Readout Chip for TPC Applications

ECAL front-end electronic status

ASIC PMm2 Pierre BARRILLON, Sylvie BLIN, Selma CONFORTI,

High speed pipelined ADC + Multiplexer for CALICE

Alternative FEE electronics for FIT.

ANALOG-TO-DIGITAL CONVERTERS

High speed 12 bits Pipelined ADC proposal for the Ecal

96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output

R&D activity dedicated to the VFE of the Si-W Ecal

Hugo França-Santos - CERN

Pedro Henrique Köhler Marra Pinto and Frank Sill Torres

Electronics for Si-W calorimeter

CALICE COLLABORATION LPC Clermont LAL Orsay Samuel MANEN Julien FLEURY

EUDET – LPC- Clermont VFE Electronics

Lesson 8: Analog Signal Conversion

SKIROC status Calice meeting – Kobe – 10/05/2007.

SKIROC status CERN – CALICE/EUDET electronic & DAQ meeting – 22/03/2007 Presented by Julien Fleury.

Signal processing for High Granularity Calorimeter

Pingli Huang and Yun Chiu

Presentation transcript:

1 Progress report on the LPSC-Grenoble contribution in micro- electronics (ADC + DAC) J-Y. Hostachy, J. Bouvier, D. Dzahini, L. Galin-Martel, E. Lagorio, F-E. Rarbi, O. Rossetto, C. Vescovi

J-Y. Hostachy et al., LPSC-Grenoble 2 Fast Digitizer for CALICE preamp Shaper_1 Shaper_10 Memory preamp Shaper_1 Shaper_10 Memory preamp Shaper_1 Shaper_10 Memory 12 bits Fast ADC MUX 32/64  1

J-Y. Hostachy et al., LPSC-Grenoble 3 Why a high speed ADC ? Multiplex 32/64 to 1 ADC High speed converter: Read all channels faster More “IDLE mode” time => Saving power digital noise source from one ADC Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% idle cycle 199ms (99%) Acquisition A/D conv. DAQ IDLE MODE Extra power saving

4 25 MHz, 12 bits, 2V pp Pipeline ADC Full 1.5 bit per stage

5 Tests of the pipeline ADC DNL: < 1 LSB INL: < 4 LSB 2V - Power supply could be reduced => Extra Power Saved - Wide noise margin σ < 0.6 LSB

6 Average Power Pulsing Budget T TC (Total Time conversion) = 40ns x 64 x 16 = 41µs MUX + ADC Power Consumption per channel = ((P ADC +P MUX ) x T TC )/200ms/64ch 141nW/channel Memory depth= 16 # of channel = 64 T c = 40 ns P ADC = 37 mW With Power pulsing P MUX = 7 mW

7 stage 1 stage 2stage bit FLASH 3 bits … datadelay+ digital correction 12 bits residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM Vin Back-endADC Front-endstage stage bits stage bit stage 10FLASH … datadelay+ digital correction 12 bits residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM residue ADC + DAC V in 2.5 bits + - x 4 S/H MDAC DEM Vin Back-endADC Front-endstage 1.5 bit stage 3 bit Flash 2.5 bit stage Bias stage A multi bit 2.5 bits 1st stage ADC Digital correction 8

J-Y. Hostachy et al., LPSC-Grenoble 8 SFDR=60dB SFDR=80dB Dynamic Element Matching effect (simulation estimate) Distortion reduced => Improvement of INL Without DEM => INL = 4 LSB With DEM => INL = 0.4 LSB Dynamic Element Matching (DEM)

9 16 bit Sigma Delta DAC 16 bits with INL = +/- 4LSB Fine results but an integrated filter is needed to generate a DC signal This is not trivial, this is why we consider another architecture “C 2 C”

J-Y. Hostachy et al., LPSC-Grenoble bit 4 MHz DAC for calibration (Segmented arrays of switched capacitors) This 12 bits is the basis to go forward to a 14 and 16 bit version. 12 bits with INL = +/- 0.4 LSB