A discussion on the Readout Schedule leading to PDR Ganesan Rajagopalan Cornell University.

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Presentation transcript:

A discussion on the Readout Schedule leading to PDR Ganesan Rajagopalan Cornell University

Top level Requirements 1200 pixels per readout line Sensitivity set by cryogenic amplifier Frequency and Bandwidth per color Bifurcation levels and dynamic range with 12 bit ADC Output complex amplitude and phase (or frequency?) and to what resolution bits?

Cryostat - Required progress up to PDR in November LNA – noise budget for all colors Determine if a new, MHz design with ST micro transistors is required. Sandy’s NXP SiGe LNA < 5K at 23K ambient Measure Noise performance at higher temperatures at optimized bias values (thermal load ~ 30mW) Detector – LNA superconducting interconnect cable Complete the evaluation of the prototype (Matt H) Design production version matching the tile design for all colors

RF sub system - Required progress up to PDR in November Design of a low cost, low noise, high dynamic range post amplifier, filter circuitry for all colors. Except the filters, other components should be common to all colors. Detailed dynamic range and linearity analysis of the entire readout chain using Agilent SystemVue

Chirp Readout - Expected progress up to PDR in November Further testing at Caltech in July Possible deployment at CSO during August CSO run Evaluation of mobile GPU for custom readout board By October 1, determine the scalability of the Chirp Readout to the low cost mobile GPU platform. Estimate schedule, budget for custom development or a suitable COTS solution.

Kintex custom board - Expected progress up to PDR in November Prototype to be delivered in May / June Testing and debugging in the lab estimated by Ryan to complete by August (quite optimistic!) Evaluating performance with MAKO in the lab September/October By October, we can get the results on the performance and suitability for CCAT adaptation.

Data transport - Desired progress up to PDR in November – Explore and decide on digitizing near the camera Locate the DAC-ADC-FPGA in a glycol cooled cabinet next to the camera EMI/RFI shielded enclosure with output on fiber GPUs and Servers can either be on the lower platform or preferably inside the Electronics/Computer Room in the Support Building we should avoid running rf coaxial cables over 30m

Data Acquisition - Desired progress up to PDR in November Demonstration of data transport on fiber via 10 Gigabit switches to Data acquisition computers ? Data rate out of the readout to be determined. Form factor, location, thermal management questions to be answered

Is this list good enough for PDR? Design (and fab) of 1200 pixel detector layout Measured results from superconducting flexible microstrip cable and LNA Kintex board working demo in the lab Chirp Readout demo on the telescope Conceptual design for the total readout system based on results from the two systems Estimated cost, power, and schedule to construction.