PXD ATCA DAQ Issues and Announcements S. Lange (Universität Gießen) Belle PXD and SVD Workshop Göttingen,

Belle II SVD and PXD, Göttingen 2012SL 2 Old Assignment (2008/09, see also TDR) 1 HalfLadder 1 DHH 1 Compute Node 1 FPGA To EVB LVDS optical 1:1:1:…

Belle II SVD and PXD, Göttingen 2012SL 3 New (Bayrischzell Workshop) DHH as ATCA module - Consequences for Assignment DHHC 5 inputs (2 inner and 3 outer) HalfLadder and DHH 4 outputs optical links to one ATCA CN DHH

Belle II SVD and PXD, Göttingen 2012SL 4 Consequences: 1. Load balancing on DHH ( )%/5 = 0.42 % 2. ATCA builds HALF-EVENTS on 1 CN (forward or backward PXD) w/o using the ATCA backplane 5 half-modules, 5 DHH but 1 optical link (6.5 Gbps) For next event: - same 5 DHH - next optical link - next CN (round robin assignment) PXD DAQ - DHH Assignment CN DHHC

Belle II SVD and PXD, Göttingen 2012SL 5 Tests at Giessen  Ongoing tests are tests beyond DESY test setup  1. Joined hardware QA checks (IHEP & Giessen) of all available CN Vers. 2 and Vers. 3 Several minor issues: power supply filter capacitor burned (12 V, 1 piece ~100 Euros), JTAG download (FPGA broken on AMC board?), oscillators (re-soldering required in many cases)  2. ATCA backplane communication (RocketIO) between several CN Tests ongoing Details to be reported at PXD/SVD DAQ and Trigger Workshop in November

Belle II SVD and PXD, Göttingen 2012SL Visit of „parlametary secretary of state“ Dr. Helge Braun Covered in both Giessen newspapers Giessener Allgemeine and Giessener Anzeiger

Belle II SVD and PXD, Göttingen 2012SL 7 Next PXD DAQ and Trigger Workshop  November University of Tokyo  Hotel block reservation at Akihabara („electric town“) 9,450 JPY per night  Plan to move from KEK to Tokyo on Sunday 18 (shops are open, so you can already buy optical cables, transistors, etc. TAXFREE)  organized by Higuchi-san  if you like to participate, please contact  strong thematical focus on DESY test

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Belle II SVD and PXD, Göttingen 2012SL 9 Data Rates (for bandwidth session)

Belle II SVD and PXD, Göttingen 2012SL 10 Data Rates (for bandwidth discussion)

Belle II SVD and PXD, Göttingen 2012SL 11 ATCA backplane subevent building (OLD) All 40 FPGAs get a data packet (even if zero hits ! empty event, but header) Main task of event building: 1 FPGA collects all packets via ATCA backplane 3-step transfer sender-FPGA ! [serial] ! switch-FPGA ! [RocketIO] ! switch-FPGA ! [serial] ! receiver-FPGA Not trivial but manageable For next event, next FPGA (round-robin) Half-Events vs. Full-Events on ATCA

Belle II SVD and PXD, Göttingen 2012SL 12 ATCA backplane subevent building (NEW) Half-event building per 1 CN Half-events stored by a CN-1of4-“master“ Task of event building: 2 FPGAs with 2 half-events need to find each other No empty headers for same event on any of the others FPGAs For next event: some other two FPGAs Need to keep bookkeeping of - non-ready half-events - half-events in use - built events