Out Line of Discussion on VLSI Design Basics The nMOS, pMOS Transistors structure Operation of MOS Transistors Simple CMOS Inverter and its Operation CMOS Inverter Structure Fabrication Steps and masks preparation Simple Lambda bases Design Rules Color Coded Stick diagrams and Mask Lay Outs

The nMOS Transistor Structure Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS) capacitor Even though gate is no longer made of metal

The nMOS Transistor Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF

The nMOS Transistor Operation Cont. When the gate is at a high voltage: There is Positive charge on gate of MOS capacitor There is Negative charge attracted to body This inverts a channel under gate to n-type Now current can flow through n-type silicon from source to Drain through induced channel, transistor is ON

The pMOS Transistor Structure Similar, but doping and voltages are reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble on gate indicates inverted behavior

Power Supply Voltage Trends GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Drive Current and Performance For digital applications, higher Id and lower C Are the key factors for CMOS circuit performance Current (Id) factor: ￭ High performance demand has driven Idsat to increase in each generation • through Vt scaling • mobility enhancement techniques (channel orientation, strained –silicon technique) ￭ In traditional CMOS inverter delay model, Idsat is overly optimistic which causes the delay lower. This is not accurate to project circuit performance. ￭ Instead of Idsat, an effective current Ideff is proposed which is more appropriate during switching of an inverter . The expected ratio of Ideff/Idsat is approx. 0.6. Ideff considers the relevance of SCE control as well as Vdd, Vt scaling

Moore’s Law 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates

CMOS Inverter A Y 1 Oct 2010

CMOS Inverter A Y 1 Oct 2010

CMOS Inverter A Y 1 Oct 2010

CMOS Fabrication CMOS transistors are fabricated on silicon wafer Oct 2010 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process Oct 2010

Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode) Use heavily doped well and substrate contacts/taps

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace

Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

Lithography Expose photoresist through n-well mask Strip off exposed photoresist

Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranha etch Necessary so resist doesn’t melt in next step

n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implantation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

Polysilicon Patterning Use same lithography process to pattern polysilicon

N-diffusion Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

N-diffusion Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

N-diffusion (cont.) Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

N-diffusion (cont.) Strip off oxide to complete patterning step

P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

Metalization Sputter on copper / aluminum over whole wafer Pattern to remove excess metal, leaving wires

IC Fabrication Furnace used to oxidize (900-1200 C) Mask exposes photoresist to light, allowing removal HF acid etch piranha acid etch diffusion (gas) or ion implantation (electric field) HF acid etch

IC Fabrication Heavy doped poly is grown with gas in furnace (chemical vapor deposition) Masked used to pattern poly Poly is not affected by ion implantation

IC Fabrication Metal is sputtered (with vapor) and plasma etched from mask

Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size scales ~X0.7 every 2 years both lateral and vertical Moore’s law Normalize feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process Today’s l = 0.01 mm (10 nanometer = 10-8 meter)

Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

Stick Diagrams VLSI design aims to translate circuit concepts onto silicon stick diagrams are a means of capturing topography and layer information - simple diagrams Stick diagrams convey layer information through colour codes (or monochrome encoding Used by CAD packages, including Microwind

Design Rules Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in silicon Interface between circuit designer and fabrication engineer Compromise designer - tighter, smaller fabricator - controllable, reproducable

Lambda Based Design Rules Design rules based on single parameter, λ Simple for the designer Wide acceptance Provide feature size independent way of setting out mask If design rules are obeyed, masks will produce working circuits Minimum feature size is defined as 2 λ Used to preserve topological features on a chip Prevents shorting, opens, contacts from slipping out of area to be contacted

Design Rules - The Reality Manufacturing processes have inherent limitations in accuracy and repeatability Design rules specify geometry of masks that provide reasonable yield Design rules are determined by experience

Problems - Manufacturing Photoresist shrinking / tearing Variations in material deposition Variations in temperature Variations in oxide thickness Impurities Variations between lots Variations across the wafer

Problems - Manufacturing Variations in threshold voltage oxide thickness ion implantation poly variations Diffusion - changes in doping (variation in R, C) Poly, metal variations in height and width -> variation in R, C Shorts and opens Via may not be cut all the way through Undersize via has too much resistance Oversize via may short

Meta Design Rules Basic reasons for design rules Rules that generate design rules Under worst case misalignment and maximum edge movement of any feature, no serious performance degradation should occur

Advantages of Generalised Design Rules Ease of learning because they are scalable, portable, durable Longlevity of designs that are simple, abstract and minimal clutter Increased designer efficiency Automatic translation to final layout

CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Select (p+,n+)

Stick Diagrams In the early days of MOS integrated circuits it was noticed that when a chip was illuminated with a white light source, each conducting layer had a distinct coloring associated with t when viewed under a microscope. This observation provided the basis for developing the technique: poly ndiff pdiff m1 m2 contact pFET nFET

An example : An Inverter

Intra-Layer Design Rules 4 Metal2 3

Transistor Layout

Via’s and Contacts

Select Layer

CMOS Inverter Layout

Layout Design Rules Transistor dimensions are in W/L ratio nMOSFETs are usually twice the width pMOSFETs are usually twice the width of nMOSFETs Holes move more slowly than electrons (must be wider to deliver same current)

Layout 3-input NAND

Cell Library (Snap Together) Layout

Layout Examples Example 1: symbolic layout for and inverter According to -based design rules, the smallest transistor channel is 2 long and 3 wide (the minimum width of diffusion region). However, in the following figure the width of transistor has been increased to 4 so that a diffusion contact (4 X 4 required) can be readily made. This 2 X 4 transistor is referred as the minimum size transistor. An inverter formed of minimum size transistors is called a minimum size inverter. Area: 42 X 15= 6302 Stick diagram

Simplified Design Rules Conservative rules to get you started

Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.01 mm process, this is 0.04 mm wide, 0.02 mm long

Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple circuit!

References Pucknell and Eshraghian Any VLSI / ULSI Design Book