Fig. 4 from Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance.

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Fig. 4 from Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance (Image 1 of 3) Hiroyuki Ota et al 2016 Jpn. J. Appl. Phys PD01 doi: /JJAP.55.08PD01

Fig. 4 from Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance (Image 2 of 3) Hiroyuki Ota et al 2016 Jpn. J. Appl. Phys PD01 doi: /JJAP.55.08PD01

Fig. 4 from Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance (Image 3 of 3) Hiroyuki Ota et al 2016 Jpn. J. Appl. Phys PD01 doi: /JJAP.55.08PD01