Instructor: Alexander Stoytchev CprE 281: Digital Logic

Logic Gates CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

Administrative Stuff This is the official class web page: If you missed the first lecture, the syllabus and other class materials are posted there.

Administrative Stuff HW1 is out It is due on Wednesday Sep 4pm. Submit it on paper before the start of the lecture

Administrative Stuff The labs and recitations start next week: Section N: Mondays, 9: :50 am (Coover Hall, room 2050) Section P: Mondays, 12:10 - 3:00 pm (Coover Hall, room 2050) Section R: Mondays, 5:10 - 8:00 pm (Coover Hall, room 2050) Section M: Tuesdays, 2:10 - 5:00 pm (Coover Hall, room 2050) Section J: Wednesdays, 8: :50 am (Coover Hall, room 2050) Section L: Thursdays, 2:10 - 5:00 pm (Coover Hall, room 2050) Section K: Thursdays, 5:10 - 8:00 pm (Coover Hall, room 2050) Section G: Fridays, 11:00 am - 1:50 pm (Coover Hall, room 2050) Section T: Fridays, 5:10 - 8:00 pm (Coover Hall, room 2050) The lab schedule is also posted on the class web page

Labs Next Week Figure 1.5 in the textbook: An FPGA board.

Labs Next Week Please download and read the lab assignment for next week before you go to your lab section. You must print the answer sheet and do the prelab before you go to the lab. The TAs will check your answers at the beginning of the lab.

Administrative Stuff No class next Monday (University Holiday)

Labs Next Week If your lab is on Mondays, i,e., Section N: Mondays, 9: :50 am (Coover Hall, room 2050) Section P: Mondays, 12:10 - 3:00 pm (Coover Hall, room 2050) Section R: Mondays, 5:10 - 8:00 pm (Coover Hall, room 2050) You will have 2 labs in one on September 8. That is, Lab #1 and Lab #2.

Labs Next Week If your recitation is on Mondays, please go to one of the other 6 recitations next week: Section M: Tuesdays, 2:10 - 3:00 pm (Coover Hall, room 2050) Section J: Wednesdays, 8:00 - 8:50 am (Coover Hall, room 2050) Section L: Thursdays, 2:10 - 3:00 pm (Coover Hall, room 2050) Section K: Thursdays, 5:10 - 6:00 pm (Coover Hall, room 2050) Section G: Fridays, 11:00 am - 11:50 am (Coover Hall, room 2050) Section T: Fridays, 5:10 - 6:00 pm (Coover Hall, room 2050) This is only for next week. And only for the recitation (first hour). You won't be able to stay for the lab as the sections are full.

x1=x0= (a) Two states of a switch S x (b) Symbol for a switch A Binary Switch [ Figure 2.1 from the textbook ]

(a) Simple connection to a battery S Battery Light x [ Figure 2.2a from the textbook ] A Light Controlled by a Switch

(b) Using a ground connection as the return path Power supply S Light x [ Figure 2.2b from the textbook ] A Light Controlled by a Switch

S Power supply S Light x1x1 x2x2 [ Figure 2.3a from the textbook ] The Logical AND function (series connection of the switches)

[ Figure 2.3b from the textbook ] The Logical OR function (parallel connection of the switches) S Power supplyS Light x1x1 x2x2

S Power supplyS Light S X1X1 X2X2 X3X3 [ Figure 2.4 from the textbook ] A series-parallel connection of the switches

S Light Power supply R x An Inverting Circuit [ Figure 2.5 from the textbook ]

x 1 x 2 x 1 x 2 + AND gate x x x 1 x 2 x 1 x 2  The Three Basic Logic Gates [ Figure 2.8 from the textbook ] OR gate NOT gate

Truth Table for NOT x x xx

x 1 x 2 x 1 x 2  Truth Table for AND

Truth Table for OR x 1 x 2 x 1 x 2 +

[ Figure 2.6b from the textbook ] Truth Tables for AND and OR

AND gate Logic Gates with n Inputs [ Figure 2.8 from the textbook ] OR gate x 1 x 2 x n x 1 x 2  x n +++ x 1 x 2 x n x 1 x 2  x n 

[ Figure 2.7 from the textbook ] Truth Table for 3-input AND and OR

x 1 x 2 x 3 fx 1 x 2 +  x 3  = [ Figure 2.8 from the textbook ] Example of a Logic Circuit Implemented with Logic Gates

x 1 x 2 x 3 fx 1 x 2 +  x 3  = [ Figure 2.8 from the textbook ] Example of a Logic Circuit Implemented with Logic Gates

Network Analysis [ Figure 2.10 from the textbook ]

Network Analysis [ Figure 2.10 from the textbook ]

Network Analysis [ Figure 2.10 from the textbook ]

Network Analysis [ Figure 2.10 from the textbook ]

Network Analysis [ Figure 2.10 from the textbook ]

Timing Diagram [ Figure 2.10 from the textbook ]

Truth Table for this Network [ Figure 2.10 from the textbook ]

Functionally Equivalent Networks [ Figure 2.10 from the textbook ]

Functionally Equivalent Networks [ Figure 2.10 from the textbook ]

The XOR Logic Gate [ Figure 2.11 from the textbook ]

The XOR Logic Gate

[ Figure 2.12 from the textbook ] Addition of Binary Numbers

[ Figure 2.12 from the textbook ] Addition of Binary Numbers

?

AND

Addition of Binary Numbers

?

XOR

Addition of Binary Numbers

a b s0s0 s1s1

The following examples came from this book

[ Platt 2009 ]

Questions?

THE END