Jun 18th 2009 SPECS system D.Charlet The SPECS field bus ACTEL APA 150 GLUE

SPECS System - June 18st 2009 D.Charlet Why SPECS  LHCb requirement Configuration system for individual boards located on the detector or crate located in the cavern. Located in radiation sensitive environment, up to 20KRad. Long distance link, up to 130m. Multi configuration (multi-drop bus, point to point). Multi standard interfaces (JTAG, I2C, parallel bus, ctrl I/O). Cheap and compact standard. Safe, fast and clean communication. A Serial Protocol for Experiment Control System

SPECS System - June 18st 2009 D.Charlet SPECS architecture  Mono Master multi-slave bus.  Bi-directional, serial, synchronous bus.  Transfert rate ~1Mbyte/s  Differential copper link  Ethernet-like link.  Master base on PCI bus. 100 m On detector Front end electronic SPEC S slav e To the very Front end chip Service box SPECSslav e Service box SPEC S slav e Top of detector Barrack s Cavern Master Board 100 m On detector Front end electronic SPEC S slav e To the very Front end chip Service box SPECSslav e Service box SPECSslav e Service box SPEC S slav e Service box SPEC S slav e Top of detector Barrack s Cavern Master Board

SPECS System - June 18st 2009 D.Charlet Frame description

SPECS System - June 18st 2009 D.Charlet PCI Specs master board

SPECS System - June 18st 2009 D.Charlet SPECS system (slave)

SPECS System - June 18st 2009 D.Charlet SPECS slave functions Features of slave:  SPECS bus: Point to point slave interface Point to point slave interface Multi drop Multi drop  Parallel interface: Parallel bus (16data, 8address) Parallel bus (16data, 8address) 32 configurable I/O lines 32 configurable I/O lines  Serial interface: Long distance I2C bus Long distance I2C bus On board I2C bus On board I2C bus JTAG bus JTAG bus 12 receiver enable 12 receiver enable 12 driver enable 12 driver enable  Interrupt: User interrupt User interrupt Transmission error Transmission error  Serial EEPROM interface: Identification register Identification register Users register Users register

SPECS System - June 18st 2009 D.Charlet Specs slave mezzanine

SPECS System - June 18st 2009 D.Charlet SPECS slave mezzanine 82mm 58mm FPGA ProASICplus from ACTEL ProASICplus from ACTEL APA150 FBGA256 APA150 FBGA256Address: Local address switch Broadcast address capability Broadcast address capability On board clock: On board clock: Crystal resonator Crystal resonator Programmable clock for SPECS readback: Programmable clock for SPECS readback: Can be divided by 2. Long distance capability: Long distance capability: Pole zero & pre-emphasis. Pole zero & pre-emphasis. Serial EEPROM interface: Serial EEPROM interface: 65Kbits capacity 65Kbits capacity JTAG bus: I2C bus: 3.3V Local I2C bus 2.5V Local I2C bus 12 Chip select Triple voting register:

SPECS System - June 18st 2009 D.Charlet Irradiation test Irradiation test on slave at the Centre de Protonthérapie d’Orsay  Irradiation up to 35Krads  7 mezzanines were irradiated in parallel  6 with specific hardware  1266 DFF/ mezzanine  192 Triple voting register  All registers on all mezzanines were continuously monitored  FPGA ACTEL PRO ASIC+ APA 150 Results  No SEL detected  7 SEU on unprotected register  No SEU on triple voting register  Re programming failure after 20Krads  FPGA failure after 35Krads  But annealing was a good surprise … Mezzanine 7 Mezzanine 4 Mezzanine 3 Mezzanine 2 Mezzanine 1 20Krd35Krd99h180h Radiation 100°C Annealing Mezzanine 5 Mezzanine 6 40Krd

SPECS System - June 18st 2009 D.Charlet Remote bus implementation

SPECS System - June 18st 2009 D.Charlet Daisy chain implementation

SPECS System - June 18st 2009 D.CharletSoftware All tools have been developed for Windows and Linux  3 different software levels: PCI drivers: developed by the PLX Company, enables communication with the PLX9030 chip on the SPECS master board via the PCI bus SpecsLib library: computes the different frames for all types of mezzanine access (Parallel, I2C, JTAG,...), for write and read operations. SpecsUser library: decodes the frames into useful data values, manages the status for the PCI accesses, also handles the more complex accesses like JTAG, I2C, DMA, and communications with the on-board ADC (DCU).  All these components interface with the PVSS software

SPECS System - June 18st 2009 D.Charlet Example of PVSS screen

SPECS System - June 18st 2009 D.Charlet Ethernet SPECS master RJ45 SPECS LVDS bus RJ45 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 DS92LV090 SN65LVDS032 RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus RJ45 SPECS LVDS bus MAC Ethernet DDR2 EEPRO M RJ 45 SPECS master Slave SOPC system Nios cpu DDR2 interface Ethernet IP EERPOM interface SPECS master Slave SPECS master Slave SPECS master Slave CYCLONE III EP3C25 Under development for LHCb upgrade.

SPECS System - June 18st 2009 D.Charlet Possible implementation for SuperB 82mm 58mm SPECS SLAVE MEZZANINE BOARD SPEC S SLAVE PRO-ASICPlus APA150 JTAG Bus I2C Bus Serial prom 65Kb s Addressswitches ChannelB[7:0] Parallel Bus ds90cv010 RJ45 Channel B decode d resonator oscillator Cd e & ctrl I/O JA Connector JB Connector I2C/JTAG_DE /12 I2C /3 JTAG /4 I2C_2.5V 2 I2C_3.3V 2 I2C/JTAG_RE /12 I/O /32 Pro g. Connector. 65Lvds32 APA_program. /7 Loc.Addr/ 6 SPECS SLAVE MEZZANINE BOARD SPEC S SLAVE PRO-ASIC3L JTAG Bus I2C Bus Serial prom 65Kb s Serial prom 65Kb s AddressswitchesAddressswitches Parallel Bus ds90cv010 RJ45 resonator oscillator Cd e & ctrl I/O JA Connector JB Connector I2C/JTAG_DE /12 SPI JTAG I2C_2.5V I2C_3.3V 2 2 I2C/JTAG_RE /12 I/O /32 Pro g. Connector. 65Lvds32 APA_program. /7 Loc.Addr/ 6 FPGA ProASIC3L from ACTEL ProASIC3L from ACTEL Address: Local address switch Broadcast address capability Broadcast address capability On board clock: On board clock: Crystal resonator Crystal resonator Programmable clock for SPECS readback: Programmable clock for SPECS readback: Can be divided by 2. Long distance capability: Long distance capability: Pole zero & pre-emphasis. Pole zero & pre-emphasis. Serial EEPROM interface: Serial EEPROM interface: 65Kbits capacity 65Kbits capacity JTAG bus JTAG bus I2C bus I2C bus SPI bus SPI bus Bus chip selecs Bus chip selecs Common to all bus Triple voting register: Triple voting register:

SPECS System - June 18st 2009 D.Charlet Possible solution for off-detector area MAC Ethernet DDR2 EEPRO M RJ 45 SOPC system Nios cpu DDR2 interface Ethernet IP EERPOM interface CYCLONE III EP3C SM connector Based on Ethernet SPECS master Parallel bus Configurable I/O I2C bus SPI bus JTAG bus

SPECS System - June 18st 2009 D.Charlet SPECS master characteristics  PCI standard: 3.3V 32-bit 33 MHz  Include: 4 SPECS masters, 4 Slaves  SPECS interface: integrated in EPC1C12 CYCLONE ALTERA FPGA (  PCI bus interface: PLX9030 (COTS)  Data buffering capability: Emitter: 1024 Kbytes Receiver : 1024 Kbytes  SPECS bus data rate programmable: :2, :4, :8, :16, :32, :64  I2C and JTAG: On front panel  On-board test capabilities 1 internal SPECS slave for each master PLX interface test register  SPECS link: Driver: B-LVDS family DS92LV090 with pole-zero cancellation Receiver: SN65LVDS032 with high common mode range