Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED CMS Tracker Two Weekly Meeting Design Update Rob Halsall et al 18 July 2001 RAL

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 ?V CMS Tracker FED 96 ADC Module TTC FPGA Opto Rx PD Array Prog Delay 1 Synch & Processing TTCrx FE 1 9 SBC DAQ SSRAM 2 X VME BSCAN FPGA 5V2.5V1.5V Dual ADC 3V Dual ADC 1 6 ?V FPGA Opto Rx PD Array 8 Synch & Processing FE 8 8 Dual ADC Dual ADC way FR Readout & Synch Control ASIC FPGA FLASH VME Interface I2C 12 way FR BScan FPGA config clk40 I2C 1 Temp Sense Temp Sense Prog Delay FPGA 1 4 Prog Delay 1 6 FPGA Prog Delay FPGA 1 4 I2C Temp Sense I2C Temp Sense 3V2.5V 1.5V 5V -5V TTS

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 HeaderData ADC Output Auto Sync(s) Frame Sync Out Status Message CMS Tracker FED System Timing Handshake Message Frame Sync In Readout Sync Out Readout Sync In Processed Message Readout Message #2234 #2233 #2220#2221 Data Burst #2220#2221 Data Data Burst #2219

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED Front End FPGA Frame_Sync_out Frame_Sync_In Readout_Sync_out Readout_Sync_In Monitor_Sync_out Monitor_Sync_In Data_stream Clock40 Reset Mode Load/Run Frame_Sync Readout_Sync ADC_Data_stream 0 ADC_Data_stream 11 Monitor_Sync & Serial_Load Full Flags Front End FPGA delay_ser_out delay_ser_in Clock40

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED Back End FPGA Frame_Sync_out0 Frame_Sync_In0 Readout_Sync_out0 Readout_Sync_In0 Monitor_Sync_out0 Monitor_Sync_In0 Data_stream0 Clock40 Reset FE0 Frame_Sync_out7 Frame_Sync_In7 Readout_Sync_out7 Readout_Sync_In7 Monitor_Sync_out7 Monitor_Sync_In7 Data_stream7 FE1 SLINK64 TTS VME Internal ADDRESS DATA IN DATA OUT QDR SSRAM TTC

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED Back End FPGA FIFO Circular Buffers Frame_Syncs Readout_Syncs Monitor_Syncs x8 TTC Rx TTS 9 ‘VME’ DECODE CONTROL & MONITOR Data_stream0 Data_stream Data In 20 Address 16 Data Out 64 SLINK 64 R/W Address Generator APV hdrs Lengths Bx,Ex Em Hdr diagnostics monitoring 80 Mhz 100 Khz MHz 40 Mhz Clock40 Reset DCM x1 x2 x4 QDR SSRAM x4 burst BSCAN 320 MHz 80 MHz Halt Lengths Header FF/PF Flags

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED Back End FPGA Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 Event N-1 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 #00000 #FFFFF Event N FE 0 FE 1 FE 7 T0T1T2 Header Ptr

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED Synch & Processing FPGA ADC 1 10 sync 11 trig2 Ped sub 11 trig3 Re-order cm sub 8 Hit finding s-data s-addr8 16 hit Packetiser 8 averages 8 header control DPM 16 No hits Sequencer-mux 88 a d a d ADC trig1 sync 11 trig2 Ped sub 11 trig3 Re-order cm sub 8 Hit finding s-data s-addr cycles hit DPM 16 No hits Sequencer-mux 88 a d a d status averages 8 headerstatus nx256x16 trig4 Synch in Synch out Synch emulator in mux Serial I/O Serial Int B’Scan Local IO Config Synch & Processing FPGA Full flags data Global reset Control Sub resets 10 Phase Registers Phase Registers 2 x 256 cycles256 cyclesnx256x16 trig1 Synch error 4x Opto Rx Delay Line Opto Rx Clock 40 MHz DLL 1x 2x 4x per adc channel phase compensation required to bring data into step

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory18 July 2001 CMS Tracker FED System Overview Board Layout ASIC adc TTCrx ASIC prog’ delay prog’ delay ’ DAQ PMC VME FE 1 DAQ TTC FE 2 FE 3 FE 4 FE 5 FE 6 FE 7 FE MByte/s 150 MByte/s/% 100 KHz 360 MByte/s B Scan 96 ADC Channels FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA FE FPGA RO FPGA VME FPGA NN Synch Reset(s) Emulator Full flags Sync error