Proposal for Gaspard Front-end electronics E. Rauly, V.Chambert 1Valérie Chambert, IPNO, 29 juin 2012.

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Presentation transcript:

Proposal for Gaspard Front-end electronics E. Rauly, V.Chambert 1Valérie Chambert, IPNO, 29 juin 2012

Outline ASIC design Front-end proposal and issues 2Valérie Chambert, IPNO, 29 juin 2012

Gaspard Valérie Chambert, IPNO, 16 février Option: Annular detectors Trapezoidal shapes for endcaps FORWARD : 3 silicon layersBACKWARD : 2 silicon layers Square : 2 silicon layers

Telescope structure forward Valérie Chambert, IPNO, 16 février (500)µm 128 N (E, t) P (PSA, E, i) 1.5mm 32 N + 32 P (E, t) P.Rosier

Channels and output signals (1) Channels : – ( )x22 1 layer – (64+64)x8 2 nd/3rd layer forward – 64x8 2nd layer backward – 64x6 2 nd layer square Valérie Chambert, IPNO, 16 février

Channels and output signals (2) 128 PSA (i+Q outputs)x (8+8+6) = 5632 fast digitisation P 128 x2X22= 5632 N (E, t) 64x2 layersx8trapezesx2outputs + (forward) 64x1 layersx8trapezesx2outputs + (backward) 64x1couchex6 squares x 2sorties (square) outputs if we don’t multiplex Valérie Chambert, IPNO, 16 février

Multiplexing Total = 5632 PSA (E or t) If we multiplex by 16 the (E, t) we get : output cables = 6224 cables If we multiplex by 16 (E, t) AND Q from 1st layer P zone, we get : 2816 (i PSA) (Q) = 3584 cables Question : can we save PSA for Q outputs ? Note : few embedded FPGA would drastically reduce the i PSA cables from 2816 to few Valérie Chambert, IPNO, 16 février

Power consumption for i and Q PSA 5632x(15mW ampli+ADC100mW) = 650 W E or t PC: 9472 x5mW= 47,36 W Total : about 700 W Valérie Chambert, IPNO, 16 février

Power consumption for i PSA i 2816x(15mW ampli+ADC100mW) = 325 W Q 2816x5mW=15W E or t PC: 9472 x5mW= 48 W Total : about 400 W to be compared to 700 W Question : can we save PSA for Q outputs ? Valérie Chambert, IPNO, 16 février

ASIC for pulse shaping : IPACI, preamplifier with both current and charge output s Q preamplier : 2 slow control switchable ranges : - 0 to 50 MeV in Silicon - 0 to 150 MeV in Silicon Current output gain : 7000 V/A Resolution : 10keV tbc Low power consumption Integrated differential outputs Note :prototype technology AMS 0.35µm BiCMOS SiGe Valérie Chambert, IPNO, 16 février

Diagram for 1 channel IPACI ASIC prototype E. RAULY, Réunion GASPARD, IPNO, 24 octobre Detector input Test input 2 Gains : Q output 0/50MeV 0/150MeV Current output Gain ×7 Q Charge output Buffer I Charge output Current output Slow control I2C or SPI Selection logic Control signals DAC_threshold Fast shaper Low walk discriminator 10 bits DAC threshold Time output

Schedule IPACI 1st run june/november 2013 IPACI tests : beginning 2014 Valérie Chambert, IPNO, 16 février

Some pending questions Space for embedded electronics Cooling Cables outputs collaborations Valérie Chambert, IPNO, 16 février