Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Design Technologies

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Views / Abstractions / Hierarchies D.Gajski, Silicon Compilation, Addison Wesley, 1988 Architectural Logic Circuit Behavioral Structural Physical device

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction N-Channel Enhancement mode MOS FET –Four Terminal Device - substrate bias –The “self aligned gate” - key to CMOS

The MOS Transistor Digital Integrated Circuits© Prentice Hall 1995 Introduction

MOS transistors Types and Symbols D S G D S G G S DD S G NMOS Enhancement NMOS PMOS Depletion Enhancement B NMOS with Bulk Contact Digital Integrated Circuits© Prentice Hall 1995 Introduction

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction The Basic Idea… »Voltage on the Gate controls the current through the source/drain path »N-Channel - N-Switches are ON when the Gate is HIGH and OFF when the Gate is LOW »P-Channel - P-Switches are OFF when the Gate is HIGH and ON when the Gate is LOW »(ON == Circuit between Source and Drain)

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Transistors as Switches G S D G S D N Switch P Switch Passes “good zeros” Passes “good ones”

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction ….The Rest of the Story... »Put them in series - both must be on to complete the circuit »Put them in parallel - either can be on to complete the circuit »Generate all sorts of Switching Functions »NOT the same as Boolean Functions.... Its RELAY logic - pin ball machines

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Series Parallel Structures N Channel: on=closed when gate is high G G GG S S SS D D D D

NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high Digital Integrated Circuits© Prentice Hall 1995 Introduction

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Series Parallel Structures(2) P Channel: on=closed when gate is low G G GG S S SS D D D D

PMOS Transistors in Series/Parallel Connection Digital Integrated Circuits© Prentice Hall 1995 Introduction

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Series Parallel Structures (3) G S D G S D N Switch P Switch Passes “good zeros” Passes “good ones” Bi-directional Switch Open Circuit, High Z S S’

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction From Switches to Boolean Functions... l Use the Switching Functions to provide paths to Vdd or GND »Vdd is the source of all Truth (Vdd = = 1) »GND is the source of all Falsehood (GND == 0) P-channelN-channel

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction The Inverter l True to False / False to True Converter 1/00/1

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction …That’s it! l This is Non-Trivial: it defines the basis for the logic abstraction which is essential for all Boolean functions. »Provide a path to VDD for 1 »Provide a path to GND for 0 »For complex functions - provide complex paths

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Four Views Logic Transistor Layout Physical

Cross-Section of CMOS Technology Digital Integrated Circuits© Prentice Hall 1995 Introduction

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Magic Layout of Inverter

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Magic “Palette” of Layers

Modern Interconnect

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Chain of Inverters Feedback loop ABCDE

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Which is which? ABCDE

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction CMOS logic structures –Static (logic) structures l Complementary structures l Pass structures l Pseudo-NMOS structures –Dynamic (logic) structures l precharged l latched l combinations –Memory structures l static l quasi-static l dynamic –I/O structures

Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Complementary Structures »Big -- 2 x N transistors for N inputs –Use the “dual” for N and P chains –Can/should be sized for maximum speed/minimum power-area »Can use well known circuit minimization techniques –Fast –Low static power dissipation –Possibly high dynamic power dissipation

Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Digital Integrated Circuits© Prentice Hall 1995 Introduction

Static CMOS Digital Integrated Circuits© Prentice Hall 1995 Introduction

Complementary CMOS Logic Style Construction (cont.) Digital Integrated Circuits© Prentice Hall 1995 Introduction

Example Gate: NAND Digital Integrated Circuits© Prentice Hall 1995 Introduction

Example Gate: NOR Digital Integrated Circuits© Prentice Hall 1995 Introduction