WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 ASIC Building Blocks for SLHC ACEOLE Mid Term Review 3 rd August 2010 CERN – Geneva, Switzerland Paulo Moreira Work package 2

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 ACEOLE fellow (ESR - 2 nd June 2009): José Pedro Cardoso Associated partner: INESC Porto / University of Porto Visiting Scientist: Dr. Jose Machado da Silva CERN: Work package leader: Paulo Moreira People

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Development of Radiation-Hard ASIC building blocks Low-Power, Low-Jitter VCXO based PLL Specifications Prototype development Including design for testability and calibration Functional and electrical characterization Irradiation testing Total Dose Single Event Upsets Final ASIC and Macro-cell Characterization Documentation Technology: 130 nm CMOS Low-noise 10 GHz VCO Specifications Modelling of radiation effects Development of a radiation robust circuits Integration of the macro-cell in the GBT10 ASIC Technology: 90 nm CMOS ASIC Building Blocks for SLHC

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 ASIC design skills Analogue and communication circuit design knowledge Training on CAE tools for ASIC design Involvement in the full ASIC design cycle: From specifications to production testing Knowledge on radiation-tolerant design methodology Design for testability methodologies Training on radiation qualification tests procedures Project Training Value

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Development of a Behavioural model for Phase-Locked Loop design Design of a Jitter measurement circuit: ~1 ps resolution Design of an Oscillator based on a Micro-Electro-Mechanical resonator Current research project : design of a VCXO based PLL: PLL features: Automatic oscillation amplitude control Digitally programmed oscillation amplitude and transconductance Built In Self Tests Detailed technical reports and presentations can be found in: R&D work

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST st Secondment period: 2009/9/7 to 2010/4/1 Partner: INESC Porto, Portugal (University of Porto, Portugal) PhD in Electrical and Computer Engineering: Seminar topics Microelectronic and Microelectromechanical technologies Test and Design for Testability Digital Communications Systems 2 nd Secondment period: 2011/02/25 to 2011/07/29 Second semester of PhD studies Secondment

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 EPLF Course – “PLLs, VCOs and Frequency Synthesizers“ 29 th June to 1 st July 2009, EPFL, Lausanne, Switzerland ESSCIRC 2009 Conference September 2009, Athens, Greece Short course: "Nanoscale CMOS analog design from devices to system" At CERN: Theoretical foundations: Study of oscillators Literature research (state of the art) Topologies: LC and XTAL Noise in oscillators CADENCE tools training: Full cycle: From schematics to extracted simulations Integrated circuit design techniques: Design and simulation (schematic and layout) of oscillators: Single-ended Differential CERN’s course: “Leaders In Science” Training

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Dr. Jose Machado da Silva 5 th and 6 th of February 2010: “Test and Design for Testability of Analogue and Mixed-Signal Circuits” (6 H) Course notes: Dr. João Canas Ferreira 25 th and 26 th 2010: “Run-Time Reconfiguration of Hardware” (6 H) Course notes: Training by Visiting Scientists

WP1 WP2 WP3 WP4 WP5 COORDINATOR WORK PACKAGE LDR RESEARCHER ACEOLE MID TERM REVIEW CERN 3 RD AUGUST 2010 Milestones and Deliverables Del. no. Titles of the Research Training Themes and description of deliverables and milestones Nature [1] [1] Dissemina tion level Delivery date [2] [2] Status TC21 Complete initial training courses (ASIC design, CAD tools, theory of phase-locked loops etc) n.a.6 Complete D21 Sign-off specification document for ASIC (IP block) RPublic6 Complete W2n Organize microelectronics user TWEPP workshop n.a.12,24,36 Complete (1/3) M21 Tape out prototype design ready for submission ORestricted18 - D22 Completion of testing and irradiation of prototype ASIC with conference report or journal publication P + RPublic27 - M22 Tape out final ASIC design ready for submission ORestricted29 - D23 Complete testing/irradiation of final ASIC and system-level integration test. Final conference report and/or journal publication D + RPublic36 - [1] The nature of the deliverable is coded as follows: R = Report, P = Prototype, D = Demonstrator, O = Other [2] For research themes 1-5 the delivery dates are measured in months from the start of individual ESR contracts.