Accellera Systems Initiative Overview April 2013 Dennis Brophy, Vice Chairman

© 2013 Accellera Systems Initiative, Inc.April 2013 Welcome Agenda  Current News  About Accellera  IEEE collaboration  Technical activities overview  SystemC Working Groups status 2

SystemC AMS 2.0 Completed  Announced 19 March 2013  Presentations on standard at ESCUG -See tuebingen.de/ESCUGWS27 -Grenoble htmlhttp:// tuebingen.de/ESCUGWS27 -Grenoble html 3 © 2013 Accellera Systems Initiative, Inc.April 2013

Multi-Language Working Group Launched  Announced 3 April 2013  Industry Invited to Join  Mission -Create a standard and functional reference for interoperability of multi- language verification environments and components. © 2013 Accellera Systems Initiative, Inc.April

To Be Announced: forums.accellera.org  Forums -Accellera System Initiative -SystemC -UCIS (Unified Coverage Interoperability Standard) -UVM (Universal Verification Methodology) -Commercial Announcements 5 © 2013 Accellera Systems Initiative, Inc.April 2013

To Be Announced: UVMWorld © 2013 Accellera Systems Initiative, Inc.April 2013

Welcome Agenda  Current News  About Accellera  IEEE collaboration  Technical activities overview  SystemC Working Groups status 7 © 2013 Accellera Systems Initiative, Inc.April 2013

© 2013 Accellera Systems Initiative, Inc.April 2013 Accellera Systems Initiative Our Mission  To provide design and verification standards required by systems, semiconductor, IP and design tool companies to enhance a front-end design automation process.  To collaborate with its community of companies, individuals and organizations in delivering the standards that lower the cost to design commercial EDA, IC and embedded system solutions. 8

© 2013 Accellera Systems Initiative, Inc.April 2013 We Have Broad Industry Support Welcome new members Altera, Broadcom, Ericsson, Maxim and NVIDIA! Corporate Members Associate Members 9

© 2013 Accellera Systems Initiative, Inc.April 2013 Promoting Accellera Systems Initiative  Feasibility study to establish “DVCon Europe” event -Evaluating industry interest via web survey  Meet at ISCUG to discuss expanded event a la “DVCon India”  ESCUG Meeting to be held at FDL Conference, September 2013 DVCon, Silicon Valley DAC, Austin DATE & ESCUG, Grenoble FDL & ESCUG, Paris ISCUG, Noida Taiwan Users Group, TBD EDS Fair, Yokohama Japan Users Group 10

© 2013 Accellera Systems Initiative, Inc.April Technical Excellence Award Janick Bergeron Mr. Bergeron is recognized for his outstanding achievements made to the Universal Verification Methodology standardization effort and the many technical advancements he has brought to the field of functional verification methodology. Candidates peer-nominated from across the organization Recognizes work by people across all working groups 11

© 2013 Accellera Systems Initiative, Inc.April 2013 Welcome Agenda  Current News  About Accellera  IEEE collaboration  Technical activities overview  SystemC Working Groups status 12

© 2013 Accellera Systems Initiative, Inc.April 2013 Strong Partnership with IEEE  IEEE Get program to allows access to EDA & IP standards worldwide -IEEE 1666 SystemC -IEEE 1685 IP-XACT -IEEE 1800 SystemVerilog  Ongoing collaboration with the IEEE Standards Association VHDL SystemC Language IP-XACT SystemVerilog (SV) Unified Power Format (UPF)‏ Property Specification Language (PSL)‏ 13

© 2013 Accellera Systems Initiative, Inc.April 2013 IEEE 1666 SystemC Downloads Plus 47,165 downloads of IEEE through January

© 2013 Accellera Systems Initiative, Inc.April 2013 IEEE 1685 IP-XACT Downloads 15

© 2013 Accellera Systems Initiative, Inc.April 2013 IEEE 1800 SystemVerilog Downloads Published on February 21, 2013 with 2,405 downloads in the first week! 16

© 2013 Accellera Systems Initiative, Inc.April 2013 Welcome Agenda  Current News  About Accellera  IEEE collaboration  Technical activities overview  SystemC Working Groups status 17

© 2013 Accellera Systems Initiative, Inc.April 2013 Accellera Systems Initiative Promotions Committee Administration Technical Committee Board of Directors SystemC TLM SystemC AMS SystemC CCI IP-XACT IP Tagging SystemC Language SystemC Synthesis SystemC Synthesis Multi Language Verilog-AMS Interface (ITC)‏ SystemRDL SystemC Verification SystemC Verification Schema WG Registers Extensions User Group Compliancy VIP (UVM) OVL UCIS 1666 SystemC 1801 UPF 1801 UPF 1076 VHDL 1800 SystemVerilog Supported IEEE Working Groups 18

© 2013 Accellera Systems Initiative, Inc.April 2013 Standards and Initiatives at a Glance 19

© 2013 Accellera Systems Initiative, Inc.April 2013 Multi-Language Working Group  Mission to create a standard and functional reference for interoperability of multi-language verification environments and components  Review requirements and develop an open source proof-of-concept for creating a standards-based approach to combine verification environments developed in different languages/frameworks  Enable introduction of UVM concepts in other environments and languages that come from legacy projects or developed with other frameworks for beneficial reasons  Accellera members encouraged to participate! Sign up at Or contact us at 20

© Accellera Systems Initiative, Inc. Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1.1 Open Verification Library (OVL) 2.7 Verilog-AMS (V-AMS) Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Unified Coverage Interoperability Standard (UCIS) 1.0 IP-XACT - Update of IEEE 1685 Intellectual Property (IP) Tagging 1.0 Multi-Language (launched) SystemC Synthesizable Subset Draft 1.3 SystemC Analog Mixed-Signal (AMS) 2.0 SystemC Configuration, Control & Inspection (CCI Requirements) SystemC Language Standard SystemRDL (launched) Transaction Level Modeling (TLM) 1.0 and 2.0 Open Source Companions: - UVM Reference Implementation 1.1d - SystemC Proof of Concept Library (POCL) - SystemC Verification Library 1.0p2 Current Standards 10 th Annual DVCon – Our flagship conference Ongoing Technical Activities 21

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC AMS 2.0 standard released! Specification SystemC CPU Interface AMS Dig RF VHDL, Verilog VHDL-AMS, Verilog-AMS SystemC AMS extensions Functional Architecture Implementation 2.0 Analog/Mixed-Signal Digital HW/SW

© 2013 Accellera Systems Initiative, Inc.April 2013 Features in SystemC AMS 2.0  The Timed Data Flow now facilitates a more dynamic behavior for AMS computations -Time steps, data rates and delays can be changed during simulations  Enables a tighter, yet efficient and time-accurate, synchronization for AMS signal processing and control systems -TDF module activations can be triggered by events from the SystemC side  Zero time steps are now possible -Suitable for DSP modelling or to perform (analog) iterations  Select the most suitable mode of operation for the signal processing functionality -Dynamic mode of operation can be combined with traditional static mode of operation using dedicated decoupling ports 23

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC AMS 2.0 in the industry  Growing interest in the industry for SystemC AMS -All supportive companies listed on the SystemC AMS quote sheet  First commercial tools supporting SystemC AMS appear in the market -EDA vendors are encouraged to support the SystemC AMS 2.0 standard in their ESL tools -Ask your preferred EDA vendor what their plans are to support SystemC AMS !  The AMS Working Group will continue to promote and explain the benefits of SystemC AMS -Ambition is to have an open source proof-of-concept made available by any of the Accellera Systems Initiative member companies -Technical update presented at DATE ESCUG Workshop on Friday March

© 2013 Accellera Systems Initiative, Inc.April 2013 Welcome Agenda  Current News  About Accellera  IEEE collaboration  Technical activities overview  SystemC Working Groups status 25

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC Language WG  Charter: -Responsible for the definition and development of the SystemC core language, the foundation on which all other SystemC libraries and functionality are built.  Current status -Released version 2.3 of the reference simulator to reflect IEEE Final package reorganized to include TLM 2.0  Plans for Discuss new concepts affecting modeling performance -Collect and resolve submitted issues as needed 26

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC Synthesis WG  Charter: To define the SystemC synthesis subset to allow synthesis of digital hardware from high- level specifications.  Current status -Release of standard targeted for Q  Plans for Review and edit draft to make sure it fully covers the SystemC LRM -Decide on remaining open items -Start work on new topics for the second version of the standard 27

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC AMS WG  Charter: The SystemC AMS Working Group is responsible for the standardization of the SystemC AMS extensions, defining and developing the language, methodology and class libraries for analog, mixed-signal and RF modeling in SystemC  Current status -Released the SystemC AMS 2.0 standard in March  Plans for Update SystemC AMS User’s Guide to explain all Dynamic TDF features, to be released H

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC Control Configuration & Inspection WG  Charter: To define standards that allow tools to interact with models in order to perform activities such as configuration, debug and analysis; target topics are: -Configuration parameters -Command and control -Registers -Save and restore  Current Status -Currently preparing a draft of the Configuration standard for public review -  Plans for Gather and incorporate feedback on the Configuration draft standard then prioritize and start working on the Control and Inspection standards 29

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC TLM WG  Charter: To define industry standard interfaces for interoperable transaction-level models supporting architectural exploration, performance analysis, building virtual platforms for software development, and functional verification.  Current status -Delivered TLM library update to conform the IEEE standard -Integrated TLM 2.0 library with the SystemC core language package 30

© 2013 Accellera Systems Initiative, Inc.April 2013 SystemC Verification WG  Charter: The Verification Working Group (VWG) is responsible for defining verification extensions to the SystemC language standard, and to enrich the SystemC reference implementation by offering an add-on SystemC Verification (SCV) library to ease the deployment of a verification methodology based on SystemC.  Current Status -Currently updating the OSCI SCV library -  Plans for To further develop and integrate verification methodologies in SystemC/TLM. 31

© 2013 Accellera Systems Initiative, Inc.April 2013 Advancing Standards Together  Share your experiences -Visit and register to post on Forums & use new UVMWorld  Show your support -Record your adoption of standards  Become an Accellera member -Join working groups 32

THANK YOU Questions? 33