28/04/2017 Forward Error Correcting (FEC) coding for SuperB serial links: a preliminary study Sergio Cavaliere Department of Physics, University of Napoli “Federico II”, Italy and INFN Sezione di Napoli, Italy e-mail: sergio.cavaliere@na.infn.it In this talk I will present some results from a preliminary study of Forward Correcting Codes for the SuperB serial links, simulations results and tools built for the purpose. It’s actually an ongoing work which will require soon a closer integration to the architecture which are being studied for the actual link.

Cavaliere - SuperB Workshop - march 2010 28/04/2017 Outline FEC codes Coding in the SuperB serial links Hamming vs. Reed Solomon Case studies Interleaving and other demons…. conclusions Cavaliere - SuperB Workshop - march 2010

A hierarchy of codes Tree codes long data blocks Iterative decoding 28/04/2017 A hierarchy of codes Forward error correction FEC Linear block codes Cyclic codes BCH codes Hamming codes Reed Solomon codes LDPC Low-Density Parity-Check Tree codes Non linear codes TCM Trellis coding modulation Turbo codes Linear: convolutional codes Tree codes long data blocks Iterative decoding memory of past behavior Block codes Treat each block of data indipendently Blocks may be almost any length LDPC codes: very large generating matrices Hamming codes Reed Solomon codes Cavaliere - SuperB Workshop - march 2010

SerDes in rad enviroments Rad hard Fixed latency under test Connections: From the FCTS to the detector From the detector to the subdetectors Layout by D. Breton LNF, Dec.09 FCTS link Tight latency requirements DS92lv18 XII SuperB Workshop - LAPP, Annecy - Mar. 18th, 2010

Which bits may be protected against errors? start stop only these bits may be protected bit 0 -- 17 20bit symbol: start, 18bit payload, stop Guaranteed transitions at the symbol boundary No encoding provided, pattern is transmitted as-it-is 61.2 MHz x 20 -> 1.2 Gbit/s, 1.1 Gbit/s user bandwidth, 1 UI = 817 ps SuperB Workshop - SLAC, Oct.09

Loss-of-lock: no recovery is possible Error injection Error flag RX recovered clock LOCK* Loss-of-Lock Lock achieved Each and every missing start/stop triggers a loss-of-lock Then, the RX automatically tries to lock on the stream Lock is (should be) guaranteed by SYNC patterns: BELLE reports a few problems with older components, no issues have been seen during our tests SuperB Workshop - SLAC, Oct.09

FEC for SuperB serial links: a general block diagram 28/04/2017 FEC for SuperB serial links: a general block diagram serdes encoder 18 18bit n n*18 decoder Data to transmit Data to distribute serial link dc balance inverse of dc balance This could be a general block diagram for the error correcting hardware. Since mostly longer data frame allow better protection and less overhead with the same protection performance we will whish probably decide to protect not a single 18 bits frame but an integer multiple of it nx18, say 18,36, 54 72 or more. Data to transmit is stored in a buffer which collects the whole data frame to be protected. This data frame is encoded adding extra bits for the protection. apr. ’17 Cavaliere - SuperB Workshop - march 2010 7 7

FEC in the coding for SuperB serial links: relevant parameters 28/04/2017 FEC in the coding for SuperB serial links: relevant parameters It is useful to simulate different formats and combination of the architecture parameters in order to choose the most convenient Relevant parameters for the evaluation are: Error correcting capacity Overhead Code_rate max_corrected = max no. of bits corrected for each message n_trasmitted = length of the code transmitted (including both message and parity bits) n_message = length of the source message (payload) apr. ’17 8 8

Cavaliere - SuperB Workshop - march 2010 28/04/2017 Hamming Codes For each m = 3,4,5…a code is built Codeword length is n = 2^m-1 bits message length k = n-m bits m Codeword length Message length Corrected bits 3 7 4 1 15 11 5 31 26 6 63 57 encoder Hamming codes are based on generalized parity: More then one parity equation is added each controllling selected bits By inversion of these equation the position of the altered bit is found Cavaliere - SuperB Workshop - march 2010 9

Cavaliere - SuperB Workshop - march 2010 28/04/2017 Reed Solomon Codes A code word is in the RS(n,k) code is a collection of n= 2m-1 m-bit symbols k of which are the message These symbols are the coefficients of a polinomial on a GF field this codeword is made of n symbols Correction is made at symbol level, not bit symbol message (k symbols) Code word length messsage length Symbols corrected n n-2 1 n-4 2 …………. …. 3 (n-1)/2 encoder codeword (n symbols) The code in the picture is RS(7,5) meaning Message: 5 symbols,code 7 symbols , correction 1 symbol - added 2 symbols Message: 15 bits - code 21 bits - correction 3 bits – added 6 bits Cavaliere - SuperB Workshop - march 2010 10

Reed Solomon codes: encoding 28/04/2017 Reed Solomon codes: encoding message polinomial generator polinomial polinomial division residual quozient code Polinomial coefficients are m bit symbols in a Galois Field GF(2^m) Operations + x are to be made in this GF Long division may be performed in a parallel architecture 28/04/2017 Cavaliere - SuperB Workshop - march 2010 11 11

Cavaliere - SuperB Workshop - march 2010 28/04/2017 GBT solutions for LHC Overhead 37.5% (25%) ecc 10 % (symbols) Overhead 50 % (40%) ecc 14.3 % (symbols) Picture and data from: An Error-Correcting Line Code for a HEP Rad-Hard Multi-GigaBit Optical Link G. Papotti a, b, A. Marchioro a, P. Moreira a a CERN, 1211 Geneva 23, Switzerland b Dept. of Information Engineering, Università di Parma, Italy Cavaliere - SuperB Workshop - march 2010 12

Hamming codes and Reed Solomon codes: a comparison 28/04/2017 Hamming codes and Reed Solomon codes: a comparison Hamming codes are optimal for a given length n : minimum redundancy for single error correction simple and fast encoding/decoding single error detection Reed Solomon codes multiple error correction with moderate overhead complex and slow encoding/decoding Cavaliere - SuperB Workshop - march 2010 13

System level block diagram 28/04/2017 System level block diagram Parameters of the system Size of the message in multiple of 18 bits Length of the balanced symbol no. of bits for the protection of the balancing hardware parity bits or symbols to add to grant protection possibility of combining more different codes hardware complexity Explore the space of the possible solutions in order to detect the most suitable Allow easily evaluating different alternatives Cavaliere - SuperB Workshop - march 2010 14

Hamming codes: generation of suitable codes and choice 28/04/2017 Hamming codes: generation of suitable codes and choice red = unbalanced codes blue = balanced codes test code True Hamming codes GBT coding A computer generated map of all suitable combination of Hamming codes best codes apr. ’17 15 Cavaliere - SuperB Workshop - march 2010 15

Hamming codes: features of the selected test code 28/04/2017 Hamming codes: features of the selected test code trasmitted a frame of 2x18 bit=36bit no polarity control codes 2 x H(15,11) + Hs(6,3) {from H(7,4)} serdes 18 36 bit 18bit n=2 2*18 Data to transmit 11 buffer & scrambler serial link Ecc = 12 % Overhead = 44 % H(15,11) Hs(6,3) 25 bit 15 6 3 Data to distribute Buffer & descrambler encoder decoder apr. ’17 Cavaliere - SuperB Workshop - march 2010 16 16

Reed Solomon codes: generation of suitable codes and choice 28/04/2017 Reed Solomon codes: generation of suitable codes and choice GBT black=no balance Max run lenght: red=18 bit blue=36bit green=54bit magenta=72bit GBT t N trasmit blocks Cavaliere - SuperB Workshop - march 2010 17

Reed Solomon codes: overhead <40 % best ecc 28/04/2017 Reed Solomon codes: overhead <40 % best ecc black=no balance Max run length red=18 bit GBT GBT Cavaliere - SuperB Workshop - march 2010 18

Reed Solomon codes: 1st case study (balanced) 28/04/2017 Reed Solomon codes: 1st case study (balanced) 3b 144b 141b Complement block 21b 60b 7s 15s 5s 11s 15b 44b 103b msg b2s Encoder RS s2b ……Channel 8X18 bits block Decomplement block B2I Decoder RS I2B Channel…… b2s bit to symbol A frame is 8 18 bits blocks (total 144 bits) 3 bits for polarity balance on the whole message 2 codes RS(15,11 1 code RS(7,5) con t=1 e m=3. Overhead = 39,8% ECC = 13,5% Cavaliere - SuperB Workshop - march 2010 19

Reed Solomon codes: 2nd case study (unbalanced) 28/04/2017 Reed Solomon codes: 2nd case study (unbalanced) Transmit 7 blocchi 18 bit each: total = 126 bit. 6 RS(7,5) codes t=1 e m=3. Overhead = 40% ECC = 14,3% b2s bit to symbol ……Channel 7X18 bits block Channel…… 126b 15b 90b 5s b2s 7s Encoder RS 21b s2bb s2b Decoder RS msg Cavaliere - SuperB Workshop - march 2010 20

Reed Solomon codes: simulations for the two case studies 28/04/2017 Reed Solomon codes: simulations for the two case studies errored stream check Each point taken on a file made of 20000 messages Cavaliere - SuperB Workshop - march 2010 21

DC balancing: scrambling or the zero overhead solution 28/04/2017 DC balancing: scrambling or the zero overhead solution Whitens statistics of the data Scrambling is based on MLS Uses feedback shift registers Used in many applications (including GBT) Scrambling must be performed before encoding because in the descramble errors may be multiplied and the cascaded decooding may be unable to correct the added error Cavaliere - SuperB Workshop - march 2010 22 22

Interleaving: correlated data to uncorrelated by interleaving 28/04/2017 Interleaving: correlated data to uncorrelated by interleaving Useful against burst of errors (eg. CD DVD) Improves slightly the error corrction error when errors in close symbols in the same message are scattered to different messages and the corrected Symbols are re-arranged in a sequence decided by a map. The related de-interleaver uses the inverse map. May be realized controlling addresses in the data buffer by means of convolution with different delays Cavaliere - SuperB Workshop - march 2010 apr. ’17 28/04/2017 23 23 23

Cavaliere - SuperB Workshop - march 2010 28/04/2017 Conclusion Preliminary analysis of coding schemes Built tools to easily analyze alla possible architectural parameters and choose relevant parameters Filter the results by means of imposed prerequisites Carried on simulations of different codes Purposely realized logic compiler for coding/decoding architectures which will be easily interfaced to VHDL Fully RTL for Hamming codes. High level, behavioral for RS codes Guidelines for the system level implementation Cavaliere - SuperB Workshop - march 2010