Development of the readout electronics a status report Leif Jönsson Collaboration meeting Santander

February 2014: First fully bonded carrier board ready. Problems with the epoxy material for the protecting glob and the flatness of the surface. August 2014: The 1st board is sent (to Scotland) for application of the tin balls. The carrier board and tests of its functionality

Test set-up for the carrier board  Low voltage board  Lund test socket board  CERN test board  Back planes  RCU April 2014: The Lund test bench is ready Advantage of the Lund test board: more options for characterization of the carrier board.

Problems with the carrier boards 1-4 e.g. sampling clock not working, shorts between bond wires, short between power and ground Our electronics engineer, Lennart Österman, visits NOTE to superintend the bonding procedure and the mounting of components. After successful mounting, measurements were done to check the connection between the chip pad and the BGA pad. The values agreed with those measured on the packaged chips. No problems were found. June 2015Glob is applied and the carrier board is sent for tin ball application. June – JulyThe division moves to new offices within the Physics Department, which delayes the tests of board 5. July 2015Tests of carrier board 5. Main results: The sampling clock, which didn’t work on the previous 4 boards, works. A data line exhibited an unstable performance and has a somewhat deviating value compared to the packaged chip; probably due to a bad connection. Very unstable performance. A less ambitious test bench is discussed in order to exclude that the test set-up, used so far, is responsible for our problems. Progress since last year’s CM

July –AugustVacation times. Sept.- OctoberAn inspection under a microscope shows that a few bond wires are sticking up slightly through the upper surface of the glob, wheras there are others that are just slightly below the surface. The test socket is made out of metal. Action: Introduce an insulator between the the upper surface of the glob and the test socket – no improvement. In order to avoid problems due to the LV-board, the test socket board was modified to have all voltages/settings/signals from the CERN test board – no improvement. In order to avoid any possible problems caused by the test socket board and the test socket, it was decided to design an adaptor board that fits into the PGA-socket of the CERN test board and has a BGA-pattern on the upper surface onto which the carrier board can be mounted. Progress sínce last year’s CM Top side Bottom side

The present test set –up for the carrier board with mounted SALTRO-chip CERN test-board Backplanes RCU (Readout Control Unit PGA-socket Adapter board with mounted SALTRO-chip

The first test of carrier board 5 mounted on the adapter board showed that one data line didn’t have a connection. This was the only error found. The first test with readout was otherwise promising. After further tests the situation got worse and we ended up with an area with no connections. We suspected a problem with the soldering. Tests of carrier board 5 The company tried to heat up the boards to see if this gave improved connections but it didn’t. The company desoldered the carrier bord from the adapter board and remeasured the carrier board alone, obtaining the same results as from the measurements on the adaptor baord i.e. connection failures. Problems with the carrier board? We contacted a company for analysis of the carrier board. They proposed:  a non-destructive micro focus X-ray investigation to search for failures in the solder joints and  ultrasonic microscopy for investigating possible delamination. If no conclusion can be drawn: cut up the board. Such investigations can be very expensive so we need to get a bid. The board was sent back to the company for inspection. The company confirmed our measuring results and made an X-ray investigation to study the soldering quality. They couldn’t see any problem.

Present mounting procedure:  Bond the chip on the carrier board and mount the passive components.  Measure at the company that all bonding wires have contact.  Apply an epoxy glob and measure the connections again.  Send the carrier board to Scotland for application of tin balls  After arrival in Lund:  mesure the connections again  test the functionality 1) with Lund test board, carrier board inserted in the testsocket 2) using adaptorboard on the CERN test board, the adaptor board is connected via a PGA-socket to the CERN test board.

Proposed new mounting procedure:  Send several carrier boards for application of tin balls. Advantage: saves time and money.  Bond the chip on the carrier board and mount the passive components.  Measure at the company that all bonding wires have contact.  Solder the unprotected carrier board to the adaptor board. This needs a special tool for handling. Confirmed by the company that they have such a tool.  Test that all channels have connection.  Apply a capsul on the adaptor board to protect the chip. Such prototypecapsules have be fabicated by 3D-printers at DESY and Lund. The capsul can be removed and mesurements can be performed directly on the chip pads with special equipment. Such equipment is available at the Divison of Solid State Physics in Lund.  Test the functionality in Lund, using the CERN test board.  In case of problems remove the capsul and measure directly on the chip/carrier board to locate the problem. New mounting procedure

Very slow progress due to:  Competition by the LHC-upgrades  Lack of manpower  Shortage of funding  Slow turnaround by the company Major longterm problem:  Development of a new chip; no activity so far Summary of the present status

Carrier board CPLD The Multi Chip Module The design of the Multi Chip (MCM) module is essentially ready. The finalization awaits the final functionality tests of the carrier board.  8 carrier board on each MCM-board (size 25x32.5 mm2) (4 on the top side and 4 on the bottom side), mounted by soldering of small tin balls on the back side of the carrier boards  1 CPLD (size 8x8 mm2), which provies communication between the DAQ and the individual channels  4 micro-connectors on the bottom side, in order to connect to the pad plane  2 connectors on the top side for LV-supply and signal transport

The Multi Chip Module (contd.) The MCM-board is designed in High Density Interconnect (HDI) technology. This technology allows for higher routing density for both signal lines as for voltage supply. This leads to a reduction of the number of layers 16 layers compared to > 20 in conventional PCB design

We are aiming for readout via ethernet. Unfortunately, Fan Zang who started to help us with the firmware was unable to continue her work. In the meantime we have contacted the Department of Electrical Engineering at Lund University and they have a project student who is presently setting up the firmware, based on the firmware developed by Fan for the ALICE- experiment and an ethernet readout from the TOTEM-experiment. Serial readout, with an encaplulated SALTRO chip on a prototype MCM, has been tested in Brussels. The readout was performed using the ALICE DATE via the DDL optical link and with this communication between the SALTRO-chip and the CPLD as well as with the SRU could be established. However, the firmware was not adapted to our planned system, which led to corrupt data. Serial Readout

Cooling of the MCM-boards in a module Idea 1: Two thin plates of good thermal conductivity, with cut outs for the connectors, and with integrated cooling pipes for CO 2 cooling, are placed on top and bottom, respectively, of the 5x5 matrix of MCM-boards. Idea 2: Microchannel cooling: the pictures below illustrate a prototype ladder for one row of MCM-boards on the top and bottom surfaces, respectively, of a module. Simulations are needed !!!

Summary The carrier board is still not working. Conclusions we have drawn so far:  Except for a small design error at the input of the sampling clock, which has been circumvented, no other design error of the carrier board has been found.  The first four boards had serious problems.  The fifth board was initially working except for one data line. Then it demonstrated deteriorating behaviour.  The board was sent back to the company for investigation and possible re-soldering of the carrier board to the adapter board.  This didn’t bring anything so we consider to send the board for analysis to find out what the problem is.  A new monting procedure has been proposed.  The design of the MCM-board is essentially ready  The firmware for serial readout via ethernet is underway.  Ideas on cooling are proposed. Simulations are needed.