Status report 2011/7/28 Atsushi Nukariya

Progress Progresses are as follows. 1. FPGA -> Analyze data from FPGA, and some revise point is found. 2. Software -> It works correctly.

FPGA -1- ・ Test on implementation mode. -> Data generator in FPGA generates data. -> It works correctly. -> Input pulse on chip. -> Some data is seen, but some revise point is found.

FPGA -2- ・ Input pulse form is as follows. -> Input this pulse to capacitor which converts voltage to current. 3us 13us 400mV

FPGA -3- ・ Delay value is set to 1. This is minimum value which FPGA can set. -> This value determines integration time. Delay

FPGA -4- ・ Voltage is input on chip D, channel 0. -> Data which info value is 0x03 or 0x07, should be seen.(Details can be seen in status report at 28 th June, ) CHIPCHANNELFIFORESERVED 2bit 3bit1bit

FPGA -5- ・ Some result is shown. -> Serious mistakes is found. -> Busy flag is output except for chip D. ・ However, data from chip D, channel 0 and FIFO A shows some result.

FPGA -6- ・ Increase amplitude. -> Some value is bigger than previous one. -> However FPGA has serious problem, consider this topic after revising FPGA.

FPGA -7- ・ Readout order is mistake. Board Chip A Chip B Chip C Chip D Board Chip A Chip B Chip C Chip D

FPGA -8- ・ In addition to change readout order, readout part from chip is renewal. -> Previous design can be seen at status report 15 th July, ・ New design has advantage as follows. * Read data from chip with parallel processing. -> Speed up. * Forget about chip control when process data in FPGA. -> Control point is decreased and Flexibility is increased.

FPGA -9- ・ New design is as follows. -> 4 FIFOs, 4 chip controllers and multiplexer are added. FIFO Chip Controller Chip Controller Chip Controller Chip Controller MUX SiTCP FIFO

FPGA -10- ・ Chip controller follows state machine. * STOP -> No processing is occurred. * READY -> Prepare for data transmit. * RCLK_RISE -> Readout data from chip. * NEXT_DATA -> Prepare for next data. * CHANNEL_END -> Procedure for empty flag is detected. * CYCLE_END_READY -> Prepare to finish 1 cycle. * CYCLE_END -> Prepare to stop data transmit. ・ In chip controller, info is added. ・ When state is CYCLE_END, 0x7fffff is written to FIFO.

FPGA -11- ・ State machine diagram is as follows.

FPGA -12- ・ Simulation is conducted. -> Data comes from data generator in FPGA.

FPGA -13- ・ Info outputs without problem. ・ 0x7fffff is output correctly. ・ Implementation test isn ’ t conducted yet.

Source code FPGA Debug Software Script Image Processing Software