April 22, Bit-Line Leakage Cancellation: Design and Test Automation Sudhanshu Khanna
April 22, Deliverables Bit-Line Leakage Cancellation Schematic Layout On-Chip High Speed Testing Memory BIST BOTTOM – UP DESIGN TOP – DOWN DESIGN
April 22, Goals & Constraints: L1 Cache design Achieve High Density How: More Bit-Cells, Less Periphery Achieve High Speed How: Lower Read Time L1 bit-cells use Low-V t transistors Memory-Vdd must be same as Core-Vdd => Can’t use Multi-Vdd to increase performance
April 22, Why is Bit-Line Leakage an Issue Challenges (Scaling issues) Lower I read Higher I leakage Only solution: Reduce # cells on a bit-line => Lower Density
April 22, Why is Bit-Line Leakage an Issue SA differential = V(BL) – V(BLB) If BL leaks, differential lowers (data-dependent too) More time needed to generate same differential => Lower Speed
April 22, Where is Bit-line leakage an issue? Advanced technology nodes Issue: High V t variation, high leakage Result: Impact on performance Sub-threshold memory Issue: Low I on /I off Result: Energy penalty due to higher required BL swing High Temperature Compliant Memories Alternative memories
April 22, Bit-line Leakage Cancellation Sense leakage value during pre-charge Inject opposite current during read Drawbacks: V -> I conversion inaccuracies Pre-charge to V DD – V t required Agawa et al, 2001
April 22, High Speed Testing Issues TESTER ~ 20 MHz 1 GHz Inverter OUTPUT PAD ~ 200 MHz Signal Analyzer ~ 100 MHz You can make a FAST inverter, but you cant see it work
Memory BIST BISTmode High Speed Clock External Tester (Slow Testing) Address generator FSMFSM Data generator Control generator StartDone Fail Memory
April 22, M-BIST Design Flow Algorithm Behavioral Verilog: NC-Verilog Structural Verilog: RTL Compiler Place and Route: Encounter Integration with Custom Memory: Virtuoso
April 22, Top-Down Flow Issues Faced RTL Complier Assign Statements Unused Nets connect to VDD, VSS Inputs of standard blocks e.g. Carry-In of Adder Unused bus signals: e.g. Z[4] of a bus Z[11:0] Encounter vs [ ] Virtuoso: Global Signals
April 22, Thanks for your time !