G. RizzoSVT Meeting – April, SVT Update SVT bi-weekly Meeting - April, Giuliana Rizzo Universita’ & INFN Pisa Group Organization & WBS status Update on SVT baseline configuration for TDR TDR Work schedule and Milestones: –Inputs for discussion

G. RizzoSVT Meeting – April, Detector optimization studies N. Neri Layer 0 Coordination G. Rizzo External Layers Coordination TBD Electrical System Engineer TBD Mechanical System Engineer F. Bosi SVT Convener G.Rizzo SVT – management structure (responsibility for TDR preparation) Sensors L. Bosisio Front-end Electronics V. Re HDI-Peripheral Electronics M.Citterio Testbeam S. Bettarini DAQ M. Villa

G. RizzoSVT Meeting – April, SVT contacts to the general detector groups Electronics, DAQ & Trigger (M. Villa - Bologna) Geometry Working Group (N. Neri - Pisa) Still to identify SVT contacts for: –MDI and Backgrounds –Fast Simulation –Full Simulation

G. RizzoSVT Meeting – April, SVT Work Breakdown Structure Breakdown of the main activities down to level 5 For several items a fair amount of R&D still needed: –Layer0 & beam pipe mechanics –Layer 0 technology More emphasis on Hybrid Pixel (best chance to become baseline option in TDR) Continue R&D on MAPS: very promising, can improve the Layer 0 performance. Activities funded by INFN/Regione Lazio Required Manpower estimated with the help of the groups already deeply involved in the R&D on thin pixels. Available Manpower includes contributions from: –Bologna, Milano, Pavia, Pisa, Roma III, Torino, Trieste, Trento, LBL

G. RizzoSVT Meeting – April, SVT – WBS

G. RizzoSVT Meeting – April, Summary of the SVT - WBS Request for SVT contracts (Regione Lazio funding) 1 FTE Mechanical Eng. - Pisa Design Layer0, beam-pipe and IR. Simulation with FEM Layer0, beam-pipe cooling systems. 1 FTE Electronic Eng. - Pavia Design analog and digital blocks for processing of signals silicon pixel in ultra-deep submicron CMOS technology. Power distribution in FE pixel chips, radiation damage, test fabricated chips 1 FTE Physicist - Bologna DAQ development for lab and beam tests; SVT DAQ architecture/optimization studies; Electronic board integration into a global DAQ framework; SVT trigger studies. 1 FTE Physicist (sharing with computing) – Milano GDML coding for the SVT geometry. Machine backgrounds studies for SVT. Implement SVT front end electronic response in the Geant4 simulation framework.

G. RizzoSVT Meeting – April, SVT baseline configuration for TDR Layer 0: Options considered:Striplets, CMOS MAPS, Hybrid Pixels Striplets: not so robust against background occupancy CMOS MAPS: testbeam results very promising but several issues still requires R&D: –Power distribution on large matrix (area 1 cm2) –Radiation Hardness Hybrid Pixels have the best chance to meet all the requirements for the TDR timescale (end of 2010)  concentrate the effort to have a solid design for Layer 0 based on this technology (pitch 50x50 um, redout speed and radiation hardness to cope with background rate 100 MHz/cm2 and low material budget) Details on the R&D activities in the next slides External Layers: Baseline similar to the present BaBar SVT: DSSD Layer 1 to 5 with the same radii + arch shape for L4-5 + extended coverage down to 300 mrad (FW and BW) Technology is not an issue but need to start the engineering of a realistic configuration Evaluate front-end chip (FSSR2, others?) with realistic inputs for: –background rate (could be high in L1-L2) –module dimensions/capacitive load (critical in L4-L5) Mechanics: strip module design & full support structure considering the new IR design. First meeting this week among Mech. Eng. (Pi-To-Mi)

G. RizzoSVT Meeting – April, SVT baseline configuration Layer 0: Hybrid Pixels Radius~1.5 cm, Module length~10 cm Power consumption ~ 2 W/cm2 in the active area Total material budget ~ 1% X0 Si sensor + FE chips 0.40 % X0 Al Bus + SMD comp % X0 Support & cooling < 0.3% X0 External Layers: Baseline similar to the present BaBar SVT: double sided silicon detectors 300 um thick Assume same BaBar radii for the 5 layers L1-L2-L3 barrel shape L4-L5 arch shape Extend coverage down to 300 mrad FW and BW –In BaBar it was 300 mrad FW and 520 mrad BW SuperB Interaction Region Schematic SVT superimposed CF Support with microchannels technology is within specs with material ~ 0.3% X0 40 cm 30 cm 20 cm Layer0 Layer Radius cm cm cm cm to 12.7 cm to 14.6 cm Layer Radius cm cm cm cm to 12.7 cm to 14.6 cm

G. RizzoSVT Meeting – April, Layer 0 pixel R&D activities 1. Hybrid Pixels: - Sept 2009 produce small prototype Front-End chip for hybrid pixel: –50x50 um pitch, 32x 128 pixel matrix, STMicroelectronics 130 nm –same readout architecture data push developed for MAPS with optimization: Simulation for full size matrix (256x180 pixels) should have readout efficiency ~ 98% with 100 MHz/cm2 hit rate – reoptimize analog cell (small capacitance ~ fF, high signal from MIP with fully depleted 200 um substrate) significant reduction in the analog power consumption w.r.t MAPS chip ~ 1 uA/pixel (?) Power consumption for digital section dominates ~ 1W/cm2 - Sept 2009 produce pixel sensors (ITC, IRST) - Test with beam Sept 2010: pixel sensor bump bonded to the FE chip. Bump bonding could be an issue since we will not have the full wafer for the FE chips. 2. Develop Pixel module components, hybrid pixel & MAPS (next slide) 3. Continue R&D on MAPS: - Large Matrix (APSEL5D~40 mm2 active area) in production beginning of Radiation damage studies (Co60 up to 5 Mrad, Neutron irradiation to start) - Testbeam on APSEL5D in Sept. 2010, single chip (no time for MAPS mod. integration). - Later testbeam (post TDR with MAPS module) At the time of the TDR report on progress on MAPS, possible option for performance improvements. Design Layer0 easily accessible for replacement

G. RizzoSVT Meeting – April, Plan proposed in CSN1 in Sept. 2008: build a multichip CMOS MAPS prototype module with specs close to the SuperB Layer0 requirements. Activity started  document with specs for MAPS module components. Module components very similar for Layer0 based on Hybrid Pixels. Produce a new document with specs for Hybrid Pixels components Pixel module for Layer 0

G. RizzoSVT Meeting – April, Pixel module components Pixel BUS needs: low material, many lines, high frequency (> 100 MHz), –contact started with CERN PCB shop (produce and test Al prototypes) Different options under study on Interfaces (HDI- power/signal input and data output link) & SVT data transmission Pixel module for Layer 0 Use modified EDRO board (SLIM5) with large FPGA, memory and optical links (i.e. flexible) as interface between FE chips and SuperB trigger and DAQ. Layer 0 module rates: 20 Gbit/s full rate (FE data push), 3 Gbit/s triggered rate

G. RizzoSVT Meeting – April, SVT configurations in FastSim SVT baseline configuration (as in slide 7: Layer0 hybrid pixel + Layer1-Layer5 similar to BaBar SVT) will be used by the Detector Geometry Working Group for Physics Studied. –N.Neri is working to update the SVT baseline description in FastSim (realistic evaluation of material, resolution etc) Other configurations will be evaluated using the FastSim for the optmization of the SVT internal geometry 1. Layer0 and Layer1 with hybrid pixels + BaBar SVT configuration for Layer2 – Layer 5 This could become a serious option if the background at Layer 1 location is much higher than what is quoted in the CDR. 2.Layer0 hybrid pixels with pitch 50x250 μm2 (z, r-phi) as foreseen for Atlas B-Layer upgrade. Well advanced project with specs and timescale similar to SuperB 3.Optimization of the external layers position and shape ( number of layers; radius of each layer; arch-shape, barrel- shape or disks)

G. RizzoSVT Meeting – April, TDR work schedule & Milestones - Need to be defined for the Tech Board Meeting next week (April 30) - Front-end chip for Hybrid Pixels Optimization of the readout architecture on full size matrix – May ’09 (internal) Optimization of the analog cell – May ‘09 (internal) Small prototype chip submitted ST (Sept ’09) - High resistivity pixel sensor: batch submission in Sept ‘09 (G. F. Dalla Betta) - Pixel module interfaces (inputs from M. Citterio) –Bus – HDI – Link to DAC board - MAPS (inputs from V. Re) Radiation Damage Power distribution on large matrix Apsel5D (40 mm2) in production beginning 2010 –ST vs Chartered/Tezzaron ??? - External Layers (inputs from Trieste) –Module components specs definition (sensor, fanout, front-end chip) - Mechanics (inputs from F. Bosi) Beam Pipe, Layer0 modules & suport, External Layers modules & support Mechanical Integration with IR, services - DAQ (inputs from M. Villa) - Testbeam (input from S. Bettarini) - Detector Optimization Studies (input from N. Neri)

G. RizzoSVT Meeting – April, SVT – TDR Milestones - Preliminary Prepared after the discussion during the SVT meeting. Still missing inputs about the items in green. Front-end chip for Hybrid Pixels Optimization of the readout architecture on full size matrix – May ’09 (internal) Optimization of the analog cell – June‘09 (internal) Small FE prototype chip submitted ST technology Sept High resistivity pixel sensor: High resistivity Pixel sensor batch submission Sept Pixel module interfaces (inputs needed from M. Citterio) Bus – HDI – Link to DAC board Milestones? - MAPS Radiation Damage results 12/2009 (internal?) Power distribution on large matrix 12/2009 (internal?) MAPS Apsel5d (40 mm2) choice of technology (ST vs Chartered/Tezzaron) 11/2009 Apsel5D in production first quarter of 2010 (depends on technology) (??) - External Layers Module components specs definition (sensor, fanout, front-end chip) 9/2009 First iteration June 2009 Mechanics (inputs needed from F. Bosi) milestones still to be defined Beam Pipe, Layer0 modules & suport, External Layers modules & support Mechanical Integration with IR, services - DAQ Complete design for testbeam board 12/2009 DAQ system for TDR still too many unknown (data push vs triggered, link module-DAQ board) - Testbeam Testbeam 9/2010 with large MAPS matrix + Hybrid pixel sensor connected to FE chip prototype (if bump bonding ready) - Detector Optimization Studies (inputs needed from N. Neri) Milestones?

G. RizzoSVT Meeting – April, Next SVT bi-weekly Meetings Proposal for the next meetings. Please fill free to suggest additional contributions. May, 5 –Update on Pixel module Interfaces (M.Citterio) TBC –Update on Detector Optimization Studies (N.Neri) May, 19 – FE for hybrid pixel –Update on readout architecture simulation (F. Giorgi) TBC June, 2 (Holiday)  move to June 3 –Update on Mechanics (F. Bosi) –Optimization of the analog pixel cell (V. Re) June 16 (during SuperB Workshop in Perugia) –External layers module components specs – first iteration (Trieste) –DAQ (M. Villa) –Update on background simulation (E. Paoloni) –Maps radiation damage results (L. Ratti) –+ Summary of various activities during parallel session

G. RizzoSVT Meeting – April, backup

G. RizzoSVT Meeting – April, SVT for SuperB Striplets option: mature technology, not so robust against background occupancy Marginal with background rate higher than ~ 5 MHz/cm 2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2) CMOS MAPS option : new & challenging technology sensor & readout in 50 um thick chip! Extensive R&D ongoing (SLIM5-Collaboration) on 3-well devices 50x50um 2 Hybrid Pixel Option : Viable option but requires some R&D Need to demonstrate for TDR that reduction in the front-end pitch to 50x50  m 2 and in the total material budget possible to meet Layer0 requirements More emphasis now on this option: it could become the baseline Layer0 option for the TDR in case MAPS are not considered mature enough by that time. The BaBar SVT technology is adequate for R > 3cm: use design similar to BaBar SVT Layer0 is subject to large background and needs to be extremely thin: > 5MHz/cm2, 1MRad/yr, ~ 0.5%X0

G. RizzoSVT Meeting – April,

G. RizzoSVT Meeting – April, Missing Manpower

G. RizzoSVT Meeting – April, Request for contracts & job description 1 FTE Mechanical Eng. - Pisa Design of the SVT Layer0 system detector. Design of beam-pipe and IR. Simulation with FEM of the Layer0 and beam-pipe cooling systems. 1 FTE Electronic Eng. - Pavia Design and simulate analog and digital blocks for processing of signals from SVT silicon pixel and microstrip detectors. Layout and integrate analog and digital blocks in readout chips in ultra-deep submicron CMOS technology. Test fabricated chips. Design schemes for power distribution inside chips 1 FTE Physicist - Bologna DAQ development for lab and beam tests; SVT DAQ architecture/optimization studies; Electronic board integration into a global DAQ framework; SVT trigger studies. 1 FTE Physicist (sharing with computing) – Milano GDML coding of several options for the SVT geometry. Study of the impact of the machine backgrounds on the SVT performances. Software development to simulate the front end electronic response in the Geant4 simulation framework.