Fast Full Scale Sensors Development IPHC - IRFU collaboration MIMOSA-26, EUDET beam telescope Ultimate, STAR PIXEL detector Journées VLSI 2010 Isabelle Valin

Journées VLSI /06/2010 EUDET: High resolution beam telescope Reference planes of EUDET Beam Telescope  Supported by the 6 th Framework Program of EC Specifications  Extrapolated DUT < 2 µm  Sensitive area ~ 2 cm 2 in 1 dimension ~ 2 cm (half reticule size)  Read-out speed ~ 10 kframes/s  Hit density: up to 10 6 hits/cm 2 /s MIMOSA-26: First full scale CMOS sensor with high read-out speed and integrated zero suppression  This final chip was submitted in 2008, returned from foundry early 2009 and is still being testing extensively. (DUT) x z y MIMOSA 21.5 mm 13.7 mm MIMOSA26 Active area: ~10.6 x 21.2 mm2

Journées VLSI /06/2010 MIMOSA-26 Architecture Pixel array  1152 columns x 576 rows Small pitch: 18.4 µm Large sensitive area ~ 2 cm 2 Column parallel read-out in rolling shutter mode  5 MHz, 200 ns / pixel Integration time ~ 100 µs In each pixel:  Self biased diode  Amplification + CDS  ionising radiation tolerant pixel design 1 discriminator/column with:  Offset compensation amplifier stages  Column-level Double Sampling Reference voltages (threshold)  ~ 2 cm long line  4 groups of discriminators Zero-suppression logic Serial transmission  80 MHz, LVDS Testability  Several test point implemented all along readout path CMOS 0.35 µm OPTO process Pixel array: 1152 x 576, ~ 0.7 Mpixels Pitch: 18.4 µm Active area: ~ 10.6 x 21.2 mm 2 Row sequencer, width: 365 µm 1152 column-level discriminators Zero suppression logic Current Ref. Bias DACs Control (r.o. and JTAG) PLL 8b/10b Memory IP blocks Memory management Ref. Voltages Buffering Pixels analog outputs for test

Journées VLSI /06/2010 Zero Suppression + Memories EUDET-BT condition: ~ 200 hits/frame/sensor Prototype SuZe-01 (2007) Zero suppression  Data compression factor 10 to 1000 depending on occupancy  Based on a sparse data scan algorithm to find hit pixels  18 groups of 64 columns  Find max. N states per group State: up to 4 contiguous pixel signals above the threshold will be encoded in a 2 bit state word following by address of the 1 st pixel N = 6  Find max. M states per row M = 9, overflow if > 9 states/row  Add row, status and state column addresses  Store the results in memory 2 IP Memories of 600 x 32 bits  Read/write ping-pong arrangement (continuous read-out) 1 FIFO is being filled with the current frame while1 FIFO is read out previous frame Maximum: 600 words Serial transmission  LVDS pads  Read-out frequency 80, up to 160 MHz

Journées VLSI /06/2010 MIMOSA-26 test results Lab and beam tests  Operation at 20°C  Clock 20 MHz (Analog response) and 80 MHz Noise  Temporal noise : 0.6 – 0.7 mV  FPN : 0.3 – 0.4 mV  ENC ~ e- Fake/Efficiency  Fake hit rate = probability for a single pixel to reconstruct a (fake) hit with no beam  Efficiency = tracks associated with a hit over total #tracks  Efficiency 99.5% for fake hit rate O(10 -4 ) Single point resolution  Residuals compatible with σ = 4 µm Yield  fully working ~ 80 % for Std, 75 % for 120 µm-thinned => Performances as expected 0.64 mV 0.31 mV sub-array A

Journées VLSI /06/2010 EUDET beam telescope: status and evolution 2007: prototype of telescope with 6 MIMOSA-17 as reference plans 2009: final telescope made of 6 MIMOSA-26 sensors running simultaneously at nominal speed (80 MHz)  operates since Sept R&D Plan  Large Area beam Telescope for AIDA project (EU-FP7 approved in march 2010)

Journées VLSI /06/2010 MIMOSA-26 with high resistivity EPI layer Standard EPI layer (10 Ωcm) versus high resistivity (400 Ωcm) EPI layer (fab. end 2009)  Increased depleted sensitive volume  Improved tolerance to non-ionizing radiation  fast charge collection and higher S/N (Analog calibration) Charge collection with X 55 Fe source, F=20 MHz, T=20°C, VDDA =3.3 V * S/N at seed pixel with beta 106 Ru source After non-ionizing irradiation at n eq /cm 2 EPI layerNoise (e-)Cal.Peak (ADC u.)Seed Pixel (%)Cluster 2x2 (%)Cluster 3x3 (%)S/N* STD 14 µm HR 10 µm HR 15 µm Charge collection with X 55 Fe source, F=20 MHz, T=15°C, VDDA =3.3 V * S/N at seed pixel with beta 106 Ru source EPI layerNoise (e-)Cal.Peak (ADC u.)Seed Pixel (%)Cluster 2x2 (%)Cluster 3x3 (%)S/N* STD 14 µm HR 10 µm HR 15 µm HR 20 µm

Journées VLSI /06/2010 Ultimate – STAR PIXEL IPHC-IRFU-LBNL collaboration

Journées VLSI /06/2010 STAR PIXEL Detector 2 nd phase 2013: install PIXEL detector composed of 2 MAPS layers 10 inner ladders, 30 outer ladders 10 MAPS sensors / ladder 1 st phase 2012: install prototype detector composed of 3 sectors with PHASE-1 sensors The Heavy Flavor Tracker (HFT) Heavy Flavor Tracker upgrade for the STAR experiment at the RHIC accelerator at BNL  Extend the capability of the detector in the heavy flavour domain  Required extrapolated track impact parameter resolution ~ 30 µm  Add a pixel detector composed of 2 MAPS layers At r1= 2.5 cm and r2= 8 cm Sensor spatial resolution < 10 µm Fast read-out ~200 µs/frame Small material budget ~ 0.3% X 0 /layer Air flow cooling (~30°C operation) Radiation environment ~ kRad, few n eq /cm 2 /year Replacement on a short time scale (1 day) In 3 step evolution…  2007: a MimoSTAR-2 based telescope has been constructed and performed measurements of the detector environment at STAR  2012: The engineering prototype detector with limited coverage (1/3 of the complete detector surface), equipped with PHASE-1 sensors will be installed  2013: The pixel detector composed with 2 layers of Ultimate sensors will be installed … with several generation of sensors  Analog outputs sensors: MimoSTAR-2 : 128x128 pixels, 30 µm pitch, 4 ms/frame MimoSTAR-3 (2006): 320x640 pixels, 30 µm pitch, 1.6 ms/frame  Digital outputs sensors, full reticule size: PHASE-1 (2008): 640 x 640 pixels with 30 µm pitch  In-pixel CDS and column discriminators  Binary outputs, 640 µs/frame Ultimate (2010): Final sensor  Faster and more granular sensor  Binary outputs and zero-suppression circuit

Journées VLSI /06/2010 Ultimate sensor characteristics Sensitive sensor area ~ 2x2 cm 2 Small material budget  Sensors thinned to 50 µm Single point resolution ~ 5-6 µm Air cooling  Low power dissipation ~ 100 mW/cm 2  (MIMOSA-26 : 170 mW/cm 2 ) Radiation tolerance:  Ionising radiation tolerant pixel design  High-Res EPI layer to improve the non-ionizing radiation tolerance  Trade-off between power dissipation, sp resolution and radiation tolerance => optimum pixel pitch Fast read-out:  Integration time < 200 µs Luminosity = cm -2 s -1 at RHIC_II  Hit density ~ 5x10 5 hits/s/cm 2  ~ 600 hits/frame/sensor AMS 0.35 µm process Submission planned in October 2010 Ultimate ready for production in 2011

Journées VLSI /06/2010 Ultimate chip design 3280 µm Column-level Discriminators Selectable analog outputs ~ 220 µm for Pads + Electronics Zero Suppression Pad Ring 365 µm JTAGBias-DACSeq. CtrlPLLMem. 1Mem. 2 Sequencer µm µm Pixel Array 928 rows x 960 columns Pitch: 20.7 µm Active area: ~ 3.8 cm² Extension of MIMOSA-26  Reticle size (~ 4 cm²) Ultimate design optimisation  Reduced power dissipation Vdd: 3V Optimized pixel pitch v.s. Non ionising radiation tolerance  Larger pitch: 18.4 µm => 20.7 µm  Estimated power consumption ~134 mW/cm² Shorter integration time  Integration time = µs  Improved pixel architecture Cascode amplifier Higher depletion voltage (SNR, rad. tol) 0.7 V  2V  Optimized discriminator timing diagram Reduced threshold non-uniformity  Alleviated analogue to digital coupling  SuZe condition ~ 600 hits/sensor/frame Noisy pixels: ~ 100 (10 -4 ) Higher hit density  larger memories 2 memories of 2048x32 bits  Enhanced testability Frequency distribution Input LVDS CLK at 160 MHz or 10 MHz (opt., using the internal PLL) Pixels+discris: 5 MHz (200 ns) 2 LVDS data out at 160 MHz, 2 LVDS markers

Journées VLSI /06/2010 MIMOSA-22AHR Engineering run submitted April 14th shared with IRFU  back from foundry end of June Motivation : Improve the non-ionizing radiation tolerance and SNR  Optimized pixel pitch Pitch = 18.4 µm and 20.7 µm  Improved pixel architecture Higher depletion voltage : 0.7 V  2 V Cascode amplifier  CVF x 2 This run includes also test structures in order to validate the High-Res substrate against latch-up  latch-up free memories design  latch-up free digital cells

Journées VLSI /06/2010 Butting

Journées VLSI /06/2010 Conclusion MIMOSA26: First large scale sensor with high read-out speed  ~ 2 cm 2 and 10 kframe/s  Matches EUDET beam telescope requirements  On-going performance assessment: high-res AMS version  Design base line for STAR Vx upgrade Ultimate: performances close to required Vx performances  Reticule size sensor ~ 4 cm 2  ~< 200 µs integration time  Design optimization (power consumption, radiation tolerance)  Submission in October 2010  First Data in 2013