0 /59 Nyquist Rate ADCs Dr. Hossein Shamsi ECE Dept, K.N. Toosi University of Technology

1 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

2 /59 Dual Slope (Integrating) ADC

3 /59 Dual Slope (Integrating) ADC It is simply proven that “Bout” denotes the desired output code.

4 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash & Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

5 /59 Flash ADC

6 /59 Other Issues Comparator input current results in errors in the derived reference voltages, “resistor- string bowing”.

7 /59 Interpolation

8 /59 Concept

9 /59 Example: Interpolating Factor of 4

10 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

11 /59 Flow Graph for the Successive-Approximation Approach

12 /59 D/A Converter-Based Successive- Approximation Converter

13 /59 Another Flow Graph for the Successive-Approximation Approach

14 /59 Successive Approximation Register ADC

15 /59 Implementation

16 /59 Sampling Phase (5-bit Example)

17 /59 Bit5 Test (MSB)

18 /59 Bit4 Test (Assuming bit5=0)

19 /59 Speed Estimate

20 /59 Limitations Conversion rate is N times smaller than the clock frequency. Conversion rate typically limited by finite bandwidth of RC network during sampling and bit-tests For high resolution, the binary weighted capacitor array can become quite large – E.g. 16-bit resolution, C total ~100pF for reasonable kT/C noise contribution If matching is an issue, an even larger value may be needed – E.g. if matching dictates C min =10fF, then 2 16 C min =655pF

21 /59 High Performance Example

22 /59 Low Power Example

23 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

24 /59 Algorithmic (or Cyclic) ADC

25 /59 Algorithmic (or Cyclic) ADC Signed input

26 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

27 /59 General Concept of Multi-Step Conversion EDITTED !

28 /59 Analysis EDITTED !

29 /59 Input to Fine Quantizer (Vres) Aggregate=total

30 /59 Alternative Illustration

31 /59 Limitations EDITTED !

32 /59 Input to Fine Quantizer with Gain

33 /59 An 8-bit Ideal two-step ADC

34 /59 An 8-bit two-step ADC with Digital Error Correction

35 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

36 /59 Pipeline ADC Block Diagram

37 /59 Pipeline ADC Characteristics

38 /59 Stage Analysis

39 /59 Stage Model with Ideal DAC

40 /59 "Residue Plot" (2-bit Sub-ADC)

41 /59 Upper Bound for Stage Gain Example: First stage with 2-bit sub-ADC, followed by 2-bit backend ADC D out =D+G -1 D b

42 /59 2 Different Explanation 00XX XX00 00XX XX00 XX00 00XX D: :D Output bits extraction algorithms: Both have the same result! + Output code : + : Output code EDITTED(ADDED) !

43 /59 Issue with G=2 B

44 /59 Idea #1: G slightly less than 2 B

45 /59 Idea #2: G =2 B-1

46 /59 Idea #3: G=2 B, Extended Backend Range

47 /59 Variant of Idea #2: "1.5-bit stage“ G =2 B-1

48 / bit Gain Stage

49 / bit Gain Stage non-idealities

50 /59 Block diagram of a 12-bit pipelined ADC Pipelined ADC with four 3-bit stages (each stage resolves two bits).

51 /59 Block diagram of a B×N-bit pipelined ADC

52 /59 AD9042

53 /59 Sampled data n-bit residue generator (N = 2 n )

54 /59 Pipelined ADC (composed of 2-bit gain-stages)

55 /59 Pipelined ADC (composed of 1.5-bit gain-stages)

56 / Bit Stage Implementation

57 /59 Residue Plot

58 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

59 /59 Time-Interleaved ADC