SecurOne - Design Presentation Group M1 Insik Yoon Mehul Jain Sriteja Tangeda Umang Shah Secure unique Smart Card and Card Reader Monday 26 th October Layouts of Modules

Status Finished: – Design selections – Block diagram for processes – Behavioral Verilog – Behavioral Verilog Simulations – Floorplan – Structural Verilog Simulations – Schematic and Simulations(Individual blocks and FSMs) – Layout (Individual Modules) To Do: – Testing – Simulation

D Flip Flop

XOR Gate

Mux 2:1

OR Gate

NAND 2 Gate

0 1 CLK D D Card_insert Card_read, Fp_read Dec_complete 10 Reset CLK 8 BIT COUNTER Dec_complete D CLK SRAM WE WL Freq Divider Comparator To Menu FSM 16 Bit data Initial FSM

Cadence Schematic

Simulation Waveforms

Waveforms Contd

CLK From Main Menu DISPLAY CLK 5 Bit Choice Reg-file Display 5 WE Q_b Q Q OR rd FP_SRAM 4B W1 W2 W3 W4 WL Central Server 16 D 1 0 Reset CLK 8 BIT COUNTER Encryptor CLK 16 Central_Com plete W5 W6 W7 QQ CLK W8 Update_Com plete Update FSM 5 To Central Server 16 To Smart Card WE To Smart Card

Cadence Schematic

Simulation Waveforms

Waveforms Contd

CLK From Main Menu DISPLAY CLK 5 Bit Choice Reg-file Update 5 WE Q_b Q Q rd W1 W2 W3 W4 Smart Card D 1 0 Reset CLK 8 BIT COUNTER Decryptor CLK 16 Smart_Card_ Ready W5 W6 W7 QQ CLK W8 Display/Trans action_Compl ete Display/Transaction FSM 5 Q CLK We_SC 16 To Display/Transac tion SRAM WE To Display/Trans action SRAM

Cadence Schematic

Simulation Waveform

Waveforms Contd

OR GATE Comparator_Complete Update_Complete Display_Complete Trans_Complete Exit’ W1 0 1 DISPLAY 2 to 4 Decoder 2 Update Trans Display Exit Main FSM

Cadence Schematic

Waveforms Contd

Clock Generator Schematic

UMANG

SRAM 1 BIT

WRITE DRIVER

BITLINE PRECHARGE CIRCUIT

SKEWED INVERTERS

32 BIT REGFILE

16 BIT REGFILE

5 BIT REGFILE

INSIK

1 BIT FULL ADDER

8 BIT FULL ADDER

2 x 4 DECODER

2 I/P XOR

4 I/P XOR

FREQUENCY DIVIDER

FREQUENCY DIVIDER SIMULATION

MEHUL

2 x 1 MUX

2 x 1 MUX SIMULATION

HLFF

HLFF SIMULATION

MODULO 8 COUNTER

COUNTER SIMULATION

LOAD REGISTER

SRITEJA

VoV1 V0<<<4V0>>>5V1>>>5V1<<<4 32-bit key reg 8-bit Adder K2 K0K3K bit Adder/sub Counter Complete

2 I/P AND

2 I/P OR

3 I/P AND

2 x 1 MUX

Encryptor Decryptor 4 B SRAM Comparator Choice Regfile Display SRAM 2B Trans. SRAM 2B Update FSM Display FSM Trans. FSM Initial FSMExit Main Menu FSM W1 W2 R2 Decryption_complete R1 Decrypted_Data FP_1 Compare_result 2 Write 16 FP_2 16 choice Read Display_menu choice return exit R1 Write Read Write Read encryption_complete Write Read FLOOR-PLAN

Transistor Counts BlockTransistor Count Encryption/Decryption 8000 FSMs (Including SRAMS) 3616 Comparator 620