CWRU EECS 318 EECS 318 CAD Computer Aided Design LECTURE 6: State machines Instructor: Francis G. Wolff Case Western Reserve University.

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CWRU EECS 318 EECS 318 CAD Computer Aided Design LECTURE 6: State machines Instructor: Francis G. Wolff Case Western Reserve University This presentation uses powerpoint animation: please viewshow

CWRU EECS 318 VHDL Component, Entity, and Architecture Entity Architecture i Other Concurrent Components Concurrent Boolean Equations Component Instance Component Declaration for-generate | if generate Concurrent With-Select-When When-Else

CWRU EECS 318 VHDL Components Component Declaration COMPONENT component_entity_name [ GENERIC ( { identifier: type [:= initial_value ]; } ) ] [ PORT ( { identifier: mode type; } ) ] END; [ Optional ] { repeat } Component Instance identifier : component_entity_name [ GENERIC MAP ( identifier {,identifier } ) ] [ PORT MAP ( identifier {,identifier } ) ] ; mode:= IN | OUT | INOUT type:= std_logic | std_logic_vector(n downto 0) | bit Add ; only if another identifier

CWRU EECS 318 VHDL Concurrent Statements Boolean Equations relation ::= relation LOGIC relation | NOT relation | ( relation ) LOGIC ::= AND | OR | XOR | NAND | NOR | XNOR Example: y <= NOT ( NOT (a) AND NOT (b) ) Multiplexor case statement WITH select_signal SELECT signal <= signal_value 1 WHEN select_compare 1, WHEN select_compare n ; Example: 2 to 1 multiplexor WITH s SELECT y <= a WHEN ‘0’, b WHEN OTHERS;

CWRU EECS 318 VHDL Concurrent Statements Conditionial signal assignment signal <= signal_value 1 WHEN condition 1 ELSE signal_value n WHEN condition n ; ELSE signal_value n+1 Example: Priority Encoder y <= a WHEN s=‘0’ ELSE b;

CWRU EECS 318 SR Flip-Flop (Latch) R S Q Q NAND R S Q n U Q n R S Q Q NOR R S Q n Q n U Q <= R NOR NQ; NQ <= S NOR Q; Q <= R NAND NQ; NQ <= S NAND Q;

CWRU EECS 318 SR Flip-Flop (Latch) NAND R S Q n U Q n R S Q Q R(t) Q(t) S(t) Q(t) Q(t + 5ns) 5ns With Delay Example: R <= ‘1’, ‘0’ after 10ns, ‘1’ after 30ns; S <= ‘1’; t 0 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns 40 ns R Q U U U U Q U U U S

CWRU EECS 318 Gated-Clock SR Flip-Flop (Latch Enable) S R Q Q LE Q <= (S NAND LE) NAND NQ; Asynchronous: Preset and Clear Synchronous: Set and Reset NQ <= (R NAND LE) NAND Q; CLR PS Suppose each gate was 5ns: how long does the clock have to be enabled to latch the data? Answer: 15ns Latches require that during the gated-clock the data must also be stable (i.e. S and R) at the same time

CWRU EECS 318 Rising-Edge Flip-flop

CWRU EECS 318 Rising-Edge Flip-flop logic diagram

CWRU EECS 318 Synchronous Sequential Circuit

CWRU EECS 318 Abstraction: Finite State Machine

CWRU EECS 318 FSM Representations

CWRU EECS 318 Simple Design Example

CWRU EECS 318 State Encoding

CWRU EECS 318 Logic Implementations

CWRU EECS 318 FSM Observations

CWRU EECS 318 Coke Machine Example

CWRU EECS 318 Coke Machine State Diagram

CWRU EECS 318 Coke Machine Diagram II

CWRU EECS 318 Moore Machines

CWRU EECS 318 Mealy Machines