The Slow Control System of the HADES RPC Wall Alejandro Gil on behalf of the HADES RPC group IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain IEEE-RT2009.

Slides:



Advertisements
Similar presentations
IMPLEMENTATION OF PCS FOR MONITORING THE GROUND INTEGRITY DEVICE Jennie Burns, College of Arts and Sciences, Creighton University, Omaha, NE
Advertisements

SciFi Tracker DAQ M. Yoshida (Osaka Univ.) MICE meeting at LBNL 10.Feb.2005 DAQ system for KEK test beam Hardware Software Processes Architecture SciFi.
Control Systems for Future GSI, May , 2003 Control System Requirements for the CBM detector Burkhard Kolb GSI HADES.
Hadron Physics (I3HP) activities Hadron Physics (I3HP) is part of Integrated Activity of 6’th European Framework. Contract has a form of consortium of.
An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment H.XU, Z.-A. LIU,Q.WANG, D.JIN, Inst. High Energy Physics, Beijing, W. Kühn, J. Lang, S.
Kaori Maeshima (FNAL), Muon Alignment EDR: FEB. 28, Endcap Alignment EMU Alignment DAQ Muon Alignment EDR Feb. 28, 2002 Outline: 1.Components to.
Power Supply Controller Architecture
LV boards Detector 8 m 2 6 sectors 8 m 2 6 sectors 8 m 2 6 sectors EPICS CLIENT SCS for custom hardware is also based on EPICS, with the particularity.
Proposal of new electronics integrated on the flanges for LAr TPC S. Cento, G. Meng CERN June 2014.
5 March DCS Final Design Review: RPC detector The DCS system of the Atlas RPC detector V.Bocci, G.Chiodi, E. Petrolo, R.Vari, S.Veneziano INFN Roma.
Huazhong Normal University (CCNU) Dong Wang.  Introduction to the Scalable Readout System  MRPC Readout Specification  Application of the SRS to CMB-MRPC.
Typical Microcontroller Purposes
IMPLEMENTATION OF SOFTWARE INPUT OUTPUT CONTROLLERS FOR THE STAR EXPERIMENT J. M. Burns, M. Cherney*, J. Fujita* Creighton University, Department of Physics,
TRIGGER-LESS AND RECONFIGURABLE DATA ACQUISITION SYSTEM FOR POSITRON EMISSION TOMOGRAPHY Grzegorz Korcyl 2013.
ETRAX CRIS architecture and Xilinx FPGA Peter Zumbruch Experiment control systems group GSI (KS/EE)
20/10/2008A. Alici - ALICE TOF Festival1 Electronics and data acquisition of the ALICE TOF detector A.Alici University and INFN, Bologna.
University of Calcutta CBM 1 ROC Design Issues Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay & Mr. Suman Sau.
Understanding Data Acquisition System for N- XYTER.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź LLRF review, DESY, 3-4 December 2007 Advanced.
Leo Greiner IPHC meeting HFT PIXEL DAQ Prototype Testing.
Data acquisition system for the Baikal-GVD neutrino telescope Denis Kuleshov Valday, February 3, 2015.
C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia R/O concept of the MVD demonstrator C.Schrader, S. Amar-Youcef, A. Büdenbender, M. Deveaux,
LNL 1 SLOW CONTROLS FOR CMS DRIFT TUBE CHAMBERS M. Bellato, L. Castellani INFN Sezione di Padova.
“DIRAC-PHASE-1” – Construction stage 1 at the international Facility for Antiproton and Ion Research (FAIR) at GSI, Darmstadt Task 8 - HADES1 Resistive.
The microIOC Family Gasper Pajor EPICS Collaboration Meeting Argonne National Laboratory June 2006.
Gueorgui ANTCHEVPrague 3-7 September The TOTEM Front End Driver, its Components and Applications in the TOTEM Experiment G. Antchev a, b, P. Aspell.
Xiangming Sun1PXL Sensor and RDO review – 06/23/2010 STAR XIANGMING SUN LAWRENCE BERKELEY NATIONAL LAB Firmware and Software Architecture for PIXEL L.
A. Ranieri / RPC-CMS Pre-loaded profile Synchronization & Control Board (SCB) The RPC electronics will consist of the FE board plus the Synchronization.
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
1/12/2010 R. CIARANFI 1 NEW NINO BOARD FOR RICH OLD AND NEW LOGISTIC NEW BOARD DESCRIPTION NEW MODULARITY 32 CH NEW FORM FACTOR FRONT END AREA AND DAQ.
OPERA TT MEETING BRUSSELS, April 11, 2003 Status of the OPERA DAQ Status of the OPERA DAQ D.Autiero, J.Marteau T.Descombes  informatics S.Gardien, C.Girerd,
New product introduction:
Connecting LabVIEW to EPICS network
Clara Gaspar, December 2012 Experiment Control System & Electronics Upgrade.
XLV INTERNATIONAL WINTER MEETING ON NUCLEAR PHYSICS Tiago Pérez II Physikalisches Institut For the PANDA collaboration FPGA Compute node for the PANDA.
LIGO-G9900XX-00-M LIGO II1 Why are we here and what are we trying to accomplish? The existing system of cross connects based on terminal blocks and discrete.
Electronic developments for the HADES RPC wall: overview and progress
Clara Gaspar on behalf of the ECS team: CERN, Marseille, etc. October 2015 Experiment Control System & Electronics Upgrade.
New RPC Front-End Electronics for HADES
ATLAS DCS ELMB PRR, March 4th 2002, H.J.Burckhart1 Embedded Local Monitor Board ELMB  Context  Aim  Requirements  Add-ons  Our aims of PRR.
Daniel Belver IX Workshop on RPC and Related Detectors, Mumbai February 13-16th 2008 Performances of the Front End Electronics for the HADES RPC wall in.
DAQ ELECTRONICS 18 March 2015MEG Collaboration Meeting, Tokyo Stefan Ritt.
Readout controller Block Diagram S. Hansen - CD-1 Lehman Review1 VXO Ø Det Links to 24 SiPM Front End Boards Clock Event Data USB ARM uC A D Rd Wrt 100Mbit.
Mitglied der Helmholtz-Gemeinschaft PANDA MVD Slow Control Issues Harald Kleines, Forschungszentrum Jülich, ZEA-2.
Vladimir Zhulanov for BelleII ECL group Budker INP, Novosibirsk INSTR2014, Novosibirsk 2014/02/28 1.
Trigger system for setup 2016 V. Rogov, V. Yurevich,D.Bogoslovski, S.Sergeev, O.Batenkov* LHEP JINR *V. G. Khlopin Radium Institute, St. Petersburg.
Firmware and Software for the PPM DU S. Anvar, H. Le Provost, Y.Moudden, F. Louis, E.Zonca – CEA Saclay IRFU – Amsterdam/NIKHEF, 2011 March 30.
29/05/09A. Salamon – TDAQ WG - CERN1 LKr calorimeter L0 trigger V. Bonaiuto, L. Cesaroni, A. Fucci, A. Salamon, G. Salina, F. Sargeni.
EPS HEP 2007 Manchester -- Thilo Pauly July The ATLAS Level-1 Trigger Overview and Status Report including Cosmic-Ray Commissioning Thilo.
Michael Traxler, GSI1 DAQ: Status of Upgrade Outline EU-Contract and BMBF money Readout and IPU-boards –MU V2 –TOF-Readout and IPU TRB V2 –Test-Board.
MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009.
LHCb Outer Tracker Electronics 40MHz Upgrade
Modeling event building architecture for the triggerless data acquisition system for PANDA experiment at the HESR facility at FAIR/GSI Krzysztof Korcyl.
DAQ ACQUISITION FOR THE dE/dX DETECTOR
Modeling event building architecture for the triggerless data acquisition system for PANDA experiment at the HESR facility at FAIR/GSI Krzysztof Korcyl.
Beam detectors performance during the Au+Au runs in HADES
HADES collaboration meeting XXIII GSI, Darmstadt
ECAL Front-end development
Alternative FEE electronics for FIT.
96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output
EMU Alignment DAQ Endcap Alignment Muon Alignment EDR Feb. 28, 2002
SIO-RTD RTD MODULE.
HADES Detector Control System
Table 1: The specification of the PSICM and the ePSICM Prototypes
VELO readout On detector electronics Off detector electronics to DAQ
Pierluigi Paolucci - I.N.F.N. Naples
UNIZH and EPFL at LHCb.
Commissioning of the ALICE-PHOS trigger
STAR-CBM Joint Workshop Heidelberg, Physikalisches Institut
Pierluigi Paolucci & Giovanni Polese
Presentation transcript:

The Slow Control System of the HADES RPC Wall Alejandro Gil on behalf of the HADES RPC group IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain IEEE-RT2009 MAY 2009 Beijing

OUTLINE INTRODUCTION to the HADES EXPERIMENT INTRODUCTION to the HADES EXPERIMENT EPICS EPICS SLOW CONTROL HARDWARE SLOW CONTROL HARDWARE COMMERCIAL HARDWARE COMMERCIAL HARDWARE CUSTOM MADE HARDWARE CUSTOM MADE HARDWARE FEE: FEE: TDC-READOUT BOARD TDC-READOUT BOARD SPI THRESHOLD SETTING SPI THRESHOLD SETTING 1-WIRE 1-WIRE LV AND DETECTOR LV AND DETECTOR 1-WIRE 1-WIRE HADCON BOARD HADCON BOARD SUMMARY SUMMARY

HADES EXPERIMENT Detection of electron- positron pairs produced in relativistic hadron- nucleus and nucleus- nucleus collisions with the goal of studying vector meson properties in nuclear matter, both normal and hot and compressed. Detection of electron- positron pairs produced in relativistic hadron- nucleus and nucleus- nucleus collisions with the goal of studying vector meson properties in nuclear matter, both normal and hot and compressed. Consists of several subdetectors for: Consists of several subdetectors for: Triggering Triggering Tracking Tracking Momentum reconstruction Momentum reconstruction Particle identification Particle identification High Acceptance DiElectron Spectrometer Located at GSI Helmholtzzentrum für Schwerionenforschung GmbHfacility, Darmstadt (Germany) Goal of the Hades RPC project: upgrade the low angle Time of Flight (TOF) detector Time resol < 100ps Magnet InnerMCDs OutterMCDs Rich TOF(scintillator) Shower

8 m 2 6 sectors

EPICS Is a widely used scalable control system. Is a widely used scalable control system. Allows to build huge distributed control systems Allows to build huge distributed control systems Open source Open source EPICS (Experimental Physics and Industrial Control) is used in HADES since its startup. EPICS (Experimental Physics and Industrial Control) is used in HADES since its startup. TWO READOUT CHANNELS PER CELL 374 ch/sector x 6 sectors  TOTAL: 2244 electronic channels

SCS VARIABLES Flow Gases Flow Gases High Voltage High Voltage Low Voltage Low Voltage COMMERCIAL HW COMMON GUI From different and hetereogeneous systems: From different and hetereogeneous systems: EPICS Thresholds setting Thresholds setting Temperatures Temperatures Switches Switches Analog V-I Analog V-I CUSTOM BUILT HW Front End LV Det

From different and hetereogeneous systems: From different and hetereogeneous systems: SCS VARIABLES Flow Gases Flow Gases High Voltage High Voltage Low Voltage Low Voltage COMMERCIAL HW COMMON GUI EPICS Thresholds setting Thresholds setting Temperatures Temperatures Switches Switches Analog V-I Analog V-I CUSTOM BUILT HW Front End LV Det

COMMERCIAL HW High Voltage ~5kV CAEN A ch (SY1527 crate) Standard Control Protocol Interface EPICS Genesys Power Supplies (48V DC ) Freon (85%) SF6 (15%) Isobutane (5%) Ethernet (TCP/IP) Gas flows Bronkhorst Standard PC

SCS VARIABLES Flow Gases Flow Gases High Voltage High Voltage Low Voltage Low Voltage COMMERCIAL HW COMMON GUI From different and hetereogeneous systems: From different and hetereogeneous systems: EPICS Thresholds setting Thresholds setting Temperatures Temperatures Switches Switches Analog V-I Analog V-I CUSTOM BUILT HW Front End LV Det

The SC system for the custom hardware uses a system-on-chip processors as a platform for the Slow Control System The SC system for the custom hardware uses a system-on-chip processors as a platform for the Slow Control System CUSTOM HW EPICS input output controllers run in AXIS ETRAX100LX chip processors EPICS input output controllers run in AXIS ETRAX100LX chip processors Embedded LINUX-Cris kernel Embedded LINUX-Cris kernel Possibility of designing distributed architectures with custom hardware Possibility of designing distributed architectures with custom hardware Specific devices/chips on custom made boards (DACs, Tª sensors…) ClientMEDM Channel access EPICS IOC

Low voltage system TRB MBDB To ethernet Front End Data acquisition system CUSTOM ELECTRONICS DC-DC converter 48V 5V,-5V,3.3V Commercial power supply RPC cells Detector

Low voltage system TRB MBDB To ethernet Front End Data acquisition system CUSTOM ELECTRONICS DC-DC converter 48V 5V,-5V,3.3V Commercial power supply Thresholds setting Thresholds setting Temperatures Temperatures Switches Switches Analog V-I Analog V-I DACs (Serial Peripheral Interface) 1-WIRE RPC cells Detector

TRB MBDB To ethernet Front End Temperature sensors DACS (8 chips x 8 channels) SC Variables adquired directly by the DAQ System (TRB) LTC2620(SPI) DS18B20(1-WIRE) Data acquisition system CUSTOM ELECTRONICS 5V,-5V,3.3V

32input LVDS lines General purpose TDC Readout Board: Main board of the DAQ Main board of the DAQ (128 TDC ch. timing 100ps ) ETRAX processor: ETRAX processor: Embedded LINUX-Cris Embedded LINUX-Cris 100Mbps Ethernet 100Mbps Ethernet Additional resources: FPGA (VIRTEX4) -now bypassed- FPGA (VIRTEX4) -now bypassed- TigerSharc DSP TigerSharc DSP Board Controller FPGA LVL2 queue LVL1 queue ETRAX Optical link (2Gbit/s) trigger HPTDC Optional DSP processing Ethernet HPTDC Front End DAQ Board (TRB)

TRB MBDB To ethernet Front End DACS (8 chips x 8 channels) SC Variables adquired directly by the DAQ System (TRB) LTC2620(SPI) Data acquisition system CUSTOM ELECTRONICS 5V,-5V,3.3V

Thresholds set before physics run Thresholds set before physics run SPI Thresholds setting Each 8 DACs (64 ch) connected in daisy chain (SPI) Each 8 DACs (64 ch) connected in daisy chain (SPI) ETRAX(IOCserver) All thresholds are set at the same time All thresholds are set at the same time “Preset table” and “Read table” “Preset table” and “Read table” Readback for correct programming verification Readback for correct programming verification

OUTLINE HAD:RPC:S3:M0:C0:spToFL HAD:RPC:S3:M0:C0:readToFL HAD:RPC:S3:M0:C0:DRWToFL HAD:RPC:S3:M0:C0:spToFL.DISA HAD:RPC:S3:DEFToF HAD:RPC:S3:M3:C2:ToFL HAD:RPC:3:wT BASED on MEDM BURT (Backup Restore Tool)

TRB MBDB To ethernet Front End Temperature sensors SC Variables adquired directly by the DAQ System (TRB) DS18B20(1-WIRE) Data acquisition system CUSTOM ELECTRONICS 5V,-5V,3.3V

1-Wire Temp. sensing Bus from MAXIM Bus from MAXIM Fully digital Fully digital Unique ID per device Unique ID per device (64 bit) (64 bit) 0-60ºC (+-0.5ºC) Look for specific ID Command: Read Temp. Assign received value to the corresponding EPICS record

FULL Front End DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors DAC chain DAC chain Temp Sensors Temp Sensors ETRAX (IOC server) EPICS ETRAX Client A Client F 1 24 Distributed architecture: Distributed architecture: 96 Temp Sensors 96 Temp Sensors 768 DAC chips 768 DAC chips 6144ch 6144ch 1-WIREINTERFACES:SPIETHERNET DAQDAQ

LV 48VDC TRBs MBOs MBs DBs miniMBOs

Low voltage system TRB MBDB To ethernet Front End Data acquisition system CUSTOM ELECTRONICS DC-DC converter 48V 5V,-5V,3.3V Commercial power supply RPC cells Detector

Low voltage system CUSTOM ELECTRONICS DC-DC converter 48V 5V,-5V,3.3V Commercial power supply RPC cells Detector Tª Sens: Tª Sens:1xDS18B20 ADC(4ch): ADC(4ch):8xDS2450 Dual switch: Dual switch:1xDS2413 Tª Sens: Tª Sens:12xDS18B20 Dual switch: Dual switch:2xDS Wire bus: Reduces cabling complexity Reduces cabling complexity Allows networks of even hundreds of m. Allows networks of even hundreds of m.

Location of the LV and detectors ~6m

LV: 384 ADC ch.384 ADC ch. 12 temp sensors12 temp sensors 6 switches6 switchesDetector: 72 temp sensors 72 temp sensors 12 switches 12 switches All the 1-wire devices will be controlled by only 1 control board

Custom board Custom board General purpose General purpose (designed at GSI) (designed at GSI) Processor Processor Ethernet Ethernet Linux Linux Microcontroller Microcontroller USART USART ADC ADC Digital I/O Digital I/O HADCON (Also CAN comm)

SUMMARY EPICS allows integration of many channels with a distributed architecture from many different systems: commercial and custom made DAQ readout platform used for part of the slow control (FEE) 1-wire network will be used for LV and Detector control/monitoring with a custom Hadcon board Installation is ongoing with fully operation of the detector is expected at the end of the year

Thanks for your attention