Full Adder Verilog(HO: wires/regs, always) Section 4.5 (Full adder)

Slides:

Advertisements

Similar presentations

Verilog Section 3.10 Section 4.5. Keywords Keywords are predefined lowercase identifiers that define the language constructs – Key example of keywords:

Advertisements

The Verilog Hardware Description Language

Supplement on Verilog adder examples

Synchronous Sequential Logic

EE 361 Fall 2003University of Hawaii1 Hardware Design Tips EE 361 University of Hawaii.

ELEN 468 Lecture 21 ELEN 468 Advanced Logic Design Lecture 2 Hardware Modeling.

Verilog Intro: Part 1.

Half Adder Sec Sec. 4.5, Schedule 11/13MondayCourse intro, diagnostic test 21/15Wednesday Fundamentals of digital logic design (1) (signed.

Anurag Dwivedi.  Verilog- Hardware Description Language  Modules  Combinational circuits  assign statement  Control statements  Sequential circuits.

Full Adder Section 4.5 Spring, 2014 J.Ou. Schedule 62/3MondayBinary addition: full adder 72/5WednesdayBinary addition: full adder/four-bit adder L2/6ThursdayLab.

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part3: Verilog – Part 1.

CSE 201 Computer Logic Design * * * * * * * Verilog Modeling

Lecture 12 Latches Section Schedule 3/10MondayLatches (1) /12WednesdayFlip-flops5.4 3/13ThursdayFlip-flops, D-latch 3/17MondaySpring.

Lecture 12 Latches Section , Block Diagram of Sequential Circuit gates New output is dependent on the inputs and the preceding values.

 HDLs – Verilog and Very High Speed Integrated Circuit (VHSIC) HDL  Widely used in logic design  Describe hardware  Document logic functions.

7-Segment LED Display DD: Section Mano: Section 3.10.

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu.

Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.

ECE 353 Computer Systems Lab I Verilog Hardware Description Language.

ENEE 408C Lab Capstone Project: Digital System Design Spring 2006 Class Web Site:

Advanced Verilog EECS 270 v10/23/06.

Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks.

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Building Functions.

More Examples Dataflow/Behavioral Modeling Section 4.12.

Encoder Section Outline Review: Sum of Products Encoder Priority Decoder Application of Priority Decoder.

each of these is an instantiation of “full_adder”

Verilog Intro: Part 2. Procedural Blocks There are two types of procedural blocks in Verilog. – initial for single-pass behavior: initial blocks execute.

Binary Addition Section 4.5. Binary Addition Example.

ECE 2372 Modern Digital System Design

Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.

Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.

CS 3850 Lecture 3 The Verilog Language. 3.1 Lexical Conventions The lexical conventions are close to the programming language C++. Comments are designated.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

CPEN Digital System Design

Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog.

Module 1.2 Introduction to Verilog

COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

1 COMP541 Sequential Circuits Montek Singh Feb 1, 2012.

Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.

Behavioral Modelling - 1. Verilog Behavioral Modelling Behavioral Models represent functionality of the digital hardware. It describes how the circuit.

M.Mohajjel. Structured Procedures Two basic structured procedure statements always initial All behavioral statements appear only inside these blocks Each.

Introduction to ASIC flow and Verilog HDL

Introduction to Verilog. Data Types A wire specifies a combinational signal. – Think of it as an actual wire. A reg (register) holds a value. – A reg.

Random Number Generation Section 3.10 Section 4.12.

Introduction to Verilog Section Outline Set Up the Environment Your First Verilog File Set Up the Test Bench Running the Simulation.

Multiplexers Section Topics Multiplexers – Definition – Examples – Verilog Modeling.

COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

Chapter 3 Digital Logic Structures

LECTURE V TEST BENCHES. As your projects become more complex and multiple modules are employed, it will no longer be possible to simulate them as we did.

Introduction to Verilog. Structure of a Verilog Program A Verilog program is structured as a set of modules, which may represent anything from a collection.

Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals.

Hardware Description Languages: Verilog

TODAY’S OUTLINE Introduction to Verilog Verilog coding format

Figure 8.1. The general form of a sequential circuit.

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu.

Verilog Introduction Fall

Lecture 2 Supplement Verilog-01

Verilog-HDL-3 by Dr. Amin Danial Asham.

Hardware Description Languages: Verilog

Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-I]

Introduction to Verilog

332:437 Lecture 8 Verilog and Finite State Machines

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu.

Supplement on Verilog adder examples

The Verilog Hardware Description Language

332:437 Lecture 8 Verilog and Finite State Machines

COE 202 Introduction to Verilog

Presentation transcript:

Full Adder Verilog(HO: wires/regs, always) Section 4.5 (Full adder)

Schedule 62/3MondayBinary addition: full adder 72/5Wednesday Binary addition: four-bit adder/subtractor L2/6ThursdayLab canceled 82/10MondayClass canceled 92/12WednesdayBinary multiplication

Outline Observations Wire Versus reg Using – Blocking statement – Non-Blocking Statement Full Adder

Observations V IL,V IH, V OH, V OL Power Supply of a Chip Orientation of a chip Outputs of the test bench Context of a variable

V IL,V IH, V OH, V OL

Power Supply of a Chip

Orientation of a Chip

Context of a Module Variable

Module Template module module_name (,, ) endmodule Input, output wires reg Program Body

wire

Wires (1): Connect Gates w1 connects the output of G1 to an input of G3.

Wires (2): Connect input/output ports to elements within a module IMPORTANT: wire is the only legal type on the left hand side of = in an assign statement. s and c are both wires in this example.

Error Message error!correct!

Wires (3): Not on the LHS of = or <= t_clock is a reg. This is OK.

Error Message

module half_adder_tb (X,Y); //output, wires, regs output X,Y; wire X,Y; wire S,C; reg t_X[10000:0]; reg t_Y[10000:0]; reg t_clock; reg [31:0] vectornum; integer fp; …. t_clock) begin X<=t_X[vectornum]; Y<=t_Y[vectornum]; vectornum<=vectornum+1; end ….. endmodule

More Examples on the of the wire

reg All outputs generated by the always block must be declared to be of type reg. reg is used to suggest that the values behaves like a variable that might be stored in a register.

reg

A,B, C are connected to the input ports of fig3p37 module.

module....endmodule module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule Always start the verilog program with the keyword pair module…endmodule The keyword module must always be terminated by the keyword endmodule.

module half_adder_tb (X,Y); //output, wires, regs output X,Y; reg X,Y; wire S,C; reg t_X[10000:0]; reg t_Y[10000:0]; reg t_clock; reg [31:0] vectornum; integer fp; …. t_clock) begin X<=t_X[vectornum]; Y<=t_Y[vectornum]; vectornum<=vectornum+1; end ….. endmodule

Legal Uses of reg

wire and reg are sometimes Interchangable

always statement The sensitivity list contains a list of all signals that will affect the outputs generated by the always block.

* in the sensitivity list will automatically include all signals on the right side of your statements can be used when you want your elements to change their values as one or more of its inputs change. can be used with either non-blocking statement (if you want to execute statements in parallel) or blocking statement (if you want to execute statements sequentially) module half_adder_tb (X,Y); //output, wires, regs output X,Y; reg X,Y; wire S,C; reg t_X[10000:0]; reg t_Y[10000:0]; reg t_clock; reg [31:0] vectornum; integer fp; …. t_clock) begin X<=t_X[vectornum]; Y<=t_Y[vectornum]; vectornum<=vectornum+1; end ….. endmodule

Why using (Desirable) (incorrect!)

Blocking (=)Statements “when the sensitivity list is satisﬁed, B gets A, C gets B, and D gets C.” But, by the time C gets B, B has been set to A. Likewise, by the time D gets C, C has been set to B, which, as we stated above, has been set to A. Important: Statements with = executes sequentially.

(<=) Non-Blocking Statements Important: B gets A’s value, C gets B’s old value, and D gets C’s old value

Truth Table for a Full Adder carry-in

Karnaugh Map For the Sum Bit (ES112 Review)

Karnaugh Map For the Carry-Out Bit (ES112 Review)

Implementation of a Full Adder (carry-in)