Investigation of BANSMOM System m5151117 Yumiko Kimezawa February 3, 20121RPS.

Slides:



Advertisements
Similar presentations
Philips Research ICS 252 class, February 3, The Trimedia CPU64 VLIW Media Processor Kees Vissers Philips Research Visiting Industrial Fellow
Advertisements

Chapter 5 Internal Memory
System Design Tricks for Low-Power Video Processing Jonah Probell, Director of Multimedia Solutions, ARC International.
CMPE 421 Parallel Computer Architecture MEMORY SYSTEM.
Memory Chapter 3. Slide 2 of 14Chapter 1 Objectives  Explain the types of memory  Explain the types of RAM  Explain the working of the RAM  List the.
Memory II Computer Architecture and Design Lecture 4.
1 Chapter Seven Large and Fast: Exploiting Memory Hierarchy.
Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 4: January 22, 2007 Memories.
Murali Vijayaraghavan MIT Computer Science and Artificial Intelligence Laboratory RAMP Retreat, UC Berkeley, January 11, 2007 A Shared.
1 SRAM: –value is stored on a pair of inverting gates –very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: –value is stored as a charge.
CSCE 313: Embedded Systems Multiprocessor Systems
Ethernet Bomber Ethernet Packet Generator for network analysis Oren Novitzky & Rony Setter Advisor: Mony Orbach Started: Spring 2008 Part A final Presentation.
Ethernet Bomber Ethernet Packet Generator for network analysis Oren Novitzky & Rony Setter Advisor: Mony Orbach Spring 2008 – Winter 2009 Midterm Presentation.
8-5 DRAM ICs High storage capacity Low cost Dominate high-capacity memory application Need “refresh” (main difference between DRAM and SRAM) -- dynamic.
Lecture 7 Lecture 7: Hardware/Software Systems on the XUP Board ECE 412: Microcomputer Laboratory.
Memory COMPUTER ORGANIZATION – ITC CPU (processing) Random Access Memory RAM Temporarily holds Data or Instruction 3.
1 The 8051 Microcontroller and Embedded Systems CHAPTER INTERFACING TO EXTERNAL MEMORY.
Optimization of System Performance using OpenMP m Yumiko Kimezawa May 25, 20111RPS.
Research Summary and Schedule m Yumiko Kimezawa August 1, 20121RPS.
Adding the TSE component to BANSMOM system and Software Development m Yumiko Kimezawa October 4, 20121RPS.
Chapter Two Memory organisation Examples of operating system n Windows 95/98/2000, Windows NT n Unix, Linux, n VAX/VMS IBM MVS n Novell Netware and Windows.
Real-Time HD Harmonic Inc. Real Time, Single Chip High Definition Video Encoder! December 22, 2004.
Chapter 5 Internal Memory. Semiconductor Memory Types.
MODULE 5: Main Memory.
Advanced SW/HW Optimization Techniques for Application Specific MCSoC m Yumiko Kimezawa Supervised by Prof. Ben Abderazek Graduate School of Computer.
Storage Allocation for Embedded Processors By Jan Sjodin & Carl von Platen Present by Xie Lei ( PLS Lab)
Towards the Design of Heterogeneous Real-Time Multicore System m Yumiko Kimezawa February 1, 20131MT2012.
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 7: February 6, 2012 Memories.
Towards the Design of Heterogeneous Real-Time Multicore System Adaptive Systems Laboratory, Master of Computer Science and Engineering in the Graduate.
Memory Cell Operation.
CYPRESS SEMICONDUCTOR. 2 Cypress Confidential QDR Class vs DDR III (DRAM) 8 8 DDR3 SDRAM QDR2+ SRAM Multiplexed Address Bus (Row &
Lab 2 Parallel processing using NIOS II processors
CSE378 Intro to caches1 Memory Hierarchy Memory: hierarchy of components of various speeds and capacities Hierarchy driven by cost and performance In early.
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 5: February 1, 2010 Memories.
Basic Memory Management 1. Readings r Silbershatz et al: chapters
1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.
1 Chapter Seven CACHE MEMORY AND VIRTUAL MEMORY. 2 SRAM: –value is stored on a pair of inverting gates –very fast but takes up more space than DRAM (4.
Research Progress Seminar
Additional Hardware Optimization m Yumiko Kimezawa October 25, 20121RPS.
Advanced Hardware/Software Optimization Techniques for Application Specific MCSoC m Yumiko Kimezawa Supervised by Prof. Ben Abderazek Adapted Systems.
Overview von Neumann Architecture Computer component Computer function
Ethernet Bomber Ethernet Packet Generator for network analysis
S Yumiko Kimezawa A design of the ECG prototype system for two leads November 5, 20101Preliminary presentation.
1  2004 Morgan Kaufmann Publishers Locality A principle that makes having a memory hierarchy a good idea If an item is referenced, temporal locality:
Ram is a volatile memory meaning that it can only store its contents as long as its power source is constantly maintained. SDRAM: Dynamic RAM - Inexpensive.
Advanced SW/HW Optimization Techniques for Application Specific MCSoC m Yumiko Kimezawa Supervised by Prof. Ben Abderazek Graduate School of Computer.
Memory Hierarchy David Kilgore CS 147 Dr. Lee Spring 2008.
Embedded Systems Design with Qsys and Altera Monitor Program
1June 9, 2006Connections 2006 FPGA-based Prototyping of the Multi-Level Computing Architecture presented by Davor Capalija Supervisor: Prof. Tarek S. Abdelrahman.
PRESENTED BY: MOHAMAD HAMMAM ALSAFRJALANI UFL ECE Dept. 3/31/2010 UFL ECE Dept 1 CACHE OPTIMIZATION FOR AN EMBEDDED MPEG-4 VIDEO DECODER.
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 8: February 19, 2014 Memories.
Types of RAM (Random Access Memory) Information Technology.
Block Cache for Embedded Systems Dominic Hillenbrand and Jörg Henkel Chair for Embedded Systems CES University of Karlsruhe Karlsruhe, Germany.
1 Scaling Soft Processor Systems Martin Labrecque Peter Yiannacouras and Gregory Steffan University of Toronto FCCM 4/14/2008.
January 21, 2011GT20101 Multicore SoC Architecture and Prototyping for Parallel ECG Processing s Yumiko Kimezawa Supervised by Prof. Abderazek Ben.
February 1, 2011GT20101 Multicore SoC Architecture and Prototyping for Parallel ECG Processing s Yumiko Kimezawa Supervised by Prof. Abderazek Ben.
Primary Storage The Triplets – ROM & RAM & Cache.
SLC/VER1.0/OS CONCEPTS/OCT'99
7-5 DRAM ICs High storage capacity Low cost
Types of RAM (Random Access Memory)
Computer Memory.
Local secondary storage (local disks)
The Triplets – ROM & RAM & Cache
William Stallings Computer Organization and Architecture 7th Edition
MICROPROCESSOR MEMORY ORGANIZATION
Computer System Design Lecture 9
Word Assembly from Narrow Chips
Contents Memory types & memory hierarchy Virtual memory (VM)
Take out a piece of paper
Presentation transcript:

Investigation of BANSMOM System m Yumiko Kimezawa February 3, 20121RPS

Outline Previous Work Current Work -Investigation of BANSMOM System -Requirement -Investigation of Stratix III Board Future Work February 3, 2012RPS2

Previous Work Implementation of 5-lead system Implementation of 10-lead system February 3, 2012RPS3 Logic utilization: 62% Not compiled

Investigation of BANSMOM System February 3, 2012RPS4 CPU memory -Until now Instructions and data are in the same space -Minor change Instructions and data are in different spaces Use of cache becomes efficient through separating these memories Instruction cache: Write back is not required Data cache: Write back is required Inefficient

Investigation of BANSMOM System February 3, 2012RPS5 Memory size (in 1-lead system’s case) -Master CPU instruction memory: 64Kbyte -Master CPU data memory: 32KByte -PPD CPU instruction memory: 32KByte -PPD CPU data memory: 32KByte -Shared memory: 2Kbyte Program size -Master module: 55 Kbyte (code + initialized data) -PPD module: 16 Kbyte (code + initialized data) Now, on-chip memory is used in the system CPU instruction and data memory make up a most portion of memory of the system

Requirement BANSMOM system needs a lot of cache memory February 3, 2012RPS6 Use of off-chip memory as not only shared memory but also cache memory will be required

Investigation of Stratix III Board DRAM -DDR3 SDRAM -DDR2 SDRAM -DDR SDRAM -QDRII + SRAM -QDRII SRAM -PLDRAM II February 3, 2012RPS7 Off-chip memory SRAM -QDR I/QDR II -NBT/Nobl I’m trying to investigate Memory capacity How to use off-chip memory Which memory to use

Future Work Optimization of BANSMOM system -investigate -Finish adding off-chip memory to our system February 3, 2012RPS8

Investigation of Stratix III Board Embedded memory -M9K memory block: 355 -M144K memory block: 16 -Embedded memory: 5,499 Kbit -MLAB: 1,775 Kbit February 3, 2012RPS9

Program Size 1-lead system -Master module  55 Kbyte (code + initialized data) -PPD module  16 Kbyte (code + initialized data) 2-lead system -Master module  56 Kbyte (code + initialized data) -PPD module  16 Kbyte (code + initialized data) -PPD module 2  16 Kbyte (code + initialized data) February 3, 2012RPS10

How to Optimize Software (example) January 16, 2012RPS11 MicroC/OS-II