Super BigBite DAQ & Trigger Jens-Ole Hansen Hall A Collaboration Meeting 16 December 2009

SBS DAQ Requirements Data rate driven by GEMs & Coordinate Detector Data rate driven by GEMs & Coordinate Detector –≈90,000 channels, 4-8% occupancy, 2 bytes/channel –≈15 kB event 5 kHz = 75 MB/s Add other detectors, allow for higher rates, …  must handle ≈100 MB/s Add other detectors, allow for higher rates, …  must handle ≈100 MB/s Far exceeds current Hall A capabilities Far exceeds current Hall A capabilities Need 12 GeV DAQ upgrade to meet the requirements Need 12 GeV DAQ upgrade to meet the requirements –Plan exists for Hall A –

12 GeV Upgrade DAQ Electronics Fully pipelined Fully pipelined 200 kHz L1 trigger rate capability 200 kHz L1 trigger rate capability VME64x front-end crates with support for VME64x front-end crates with support for –High-speed readout modes (2eVME, 2eSST) up to 200 MB/s –Event “blocking” (buffering, caching) - up to 200 events –Custom serial (VXS) backplane bus:  Bi-directional trigger path  Optional data path –(Trunked) Gigabit Ethernet or fiber uplinks to event builder Synchronous trigger distribution, 250 MHz ref. Clock Synchronous trigger distribution, 250 MHz ref. Clock SBS will use some of this technology + custom modules SBS will use some of this technology + custom modules

Future Front Ends (graphics from Dave Abbott) Trigger Interface (TI) CODA 2 & 3 support FADCF1TDC CPU: Intel or Motorola Linux or vxWorks Dual GigE >200 MB/s CODA 2 & 3 ROC Clock/Trigger Signal Distribution (SD) Crate Trigger Processor (CTP) (optional) VME64x/VXS Crate Trigger & Clock (via fiber) Data (via Ethernet)

SBS Trigger Considerations GMn and GEn(2) GMn and GEn(2) –BigBite with gas Cherenkov and shower: ≤ 3 kHz singles. Use as is (for both arms). No need for hardware coincidence. GEp(5): elastic H(e,e’p) GEp(5): elastic H(e,e’p) –≈60 kHz singles in electron arm (BigCal) –≈1.5 MHz singles in proton arm (SBS) –  ≥ 5 kHz raw coincidence rate. Too high. –  take advantage of spatial correlations in elastic scattering to build intelligent coincidence logic

GEp(5) Spatial-Correlations Trigger Level 1 Level 1 –≈ 100 ns –“Mark” samples in APV-25 GEM readouts –Gate Fastbus & VME –Generated by electron arm ( ≈ 60 kHz rate) Level 2 Level 2 –≈ 3 μs –Use FPGAs to detect spatial correlations between ECAL and HCAL calorimeters –Reduces rate by factor of 5 –Fast Clear FB & VME after L2 timeout  < 20% DT

GEp(5) Calorimeter Sums good coincidence noise hit

ECAL Sums x5 to ADCs “sum-8”  “sum-32” 4x(4x19)=

HCAL Sums 12-bit FADCs CPUCPU TITI HCALHCAL x16 x8 x200 16x8 bits/16 ns = 8 Gb/s per FADC “sum-16” to FPGAs 4x(7x7)=

FPGA Coincidence Logic For each calorimeter section (4x): CAEN 1495 FPGA VME module (128 inputs) VME  76 x ECAL “sum-32” ≈3 μs must delay ≈3 μs Smart HCAL custom VMEx 49 x HCAL “sum-16”

Conclusions SBS Data Acquisition rather challenging SBS Data Acquisition rather challenging –Up to 100 MB/s data rate –Pipelined electronics –Custom modules GEp(5) Trigger similarly challenging GEp(5) Trigger similarly challenging –Digital summing logic for HCAL –FPGA coincidence logic Need experience, R&D Need experience, R&D