© 2008 Altera Corporation—Public 40-nm Stratix IV FPGAs Innovation Without Compromise

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 Stratix IV FPGAs: A Closer Look Highest density  Up to 680K logic elements (LEs)  Up to 22.4-Mbits internal RAM  Up to 1, x 18 multipliers Highest bandwidth and performance  Up to 48 transceivers operating up to 8.5 Gbps  Up to 4 x8 hard intellectual property (IP) blocks for PCI Express Gen 1 and Gen 2  Up to 748 giga multiply-accumulate operations per second (GMACS) digital signal processing (DSP) performance  2 speed grade performance advantage Lowest power  Programmable Power Technology  Quartus ® II PowerPlay technology  40-nm process benefits including 0.9V core voltage Seamless FPGA prototyping to HardCopy ASIC production Quartus II 8.0: #1 in Performance and Productivity Highest density, highest performance AND lowest power

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 33 DeviceLEs Transceivers (8.5, 3.2 Gbps 1 ) LVDSI/Os Memory (Mbits) Multipliers (18x18) Stratix IV GX device EP4SGX7070K8 (8,0) EP4SGX110110K16 (16,0) EP4SGX230230K36 (24,12) ,288 EP4SGX290290K 36 (24,12) EP4SGX360360K 36 (24,12) ,040 EP4SGX530530K48 (32,16) ,024 Stratix IV E device EP4SE110110K EP4SE230230K ,288 EP4SE290290K EP4SE360360K ,040 EP4SE530530K ,024 EP4SE680680K-1321, ,360 Stratix IV FPGA Device Family Plan Notes: 1) Full duplex serial transceivers 2) Details on roadmap to faster speed transceivers available upon request

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 44 Notes: FlipChip ball-grid array (BGA) with 1.0-mm pitch Total I/O, LVDS, transceiver counts Stratix IV GX Device Package Plan Device F780 (29 mm) F1152 (35 mm) F1152 (35 mm) F1517 (40 mm) F1932 (45 mm) EP4SGX70368, 28, 8 EP4SGX110368, 28, 8368, 28, 16 EP4SGX230 1 st rollout device 368, 28, 8560, 44, 16560, 44, , 88, 36 EP4SGX290288, 0, 16560, 44, 16560, 44, , 88, , 88, 36 EP4SGX360288, 0, 16560, 44, 16560, 44, , 88, , 88, 36 EP4SGX530 2 nd rollout device 560, 44, , 88, , 98, 48 Pin migration Details subject to change

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5 Notes: FlipChip ball-grid array (BGA) with 1.0-mm pitch LVDS I/O count represents full duplex channels and are included in the total I/O count Details subject to change Device F780 (29 mm) F1152 (35 mm) F1517 (40 mm) F1760 (43 mm) Stratix III device EP3SL200960, 112 EP3SE260960, 112 EP3SL340960, 1121,104, 132 Stratix IV device EP4SE110480, 56 EP4SE230480, 56 EP4SE290480, 56736, 88864, 88 EP4SE360480, 56736, 88864, 88 EP4SE530736, 88960, 112 EP4SE680736, 88960, 1121,104, 132 Stratix IV E Device Package Plan

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 66 Protocol Support ProtocolHardCopy IV ASICsStratix IV FPGAs 3G Protocols PCI Express Gen 1 (x1, x2, x4, x8), PCI Express Cable Serial RapidIO ® (1x, 4x) Gigabit Ethernet, XAUI (IEEE 802.3ae), HiGig+ 3G Basic (proprietary), 3G SerialLite II CPRI v3.0, OBSAI v2.0/RP3-01 v4.0 SONET OC-3/12/48, GPON SATA, SAS SD, HD and 3G SDI, ASI Serial Data Converter (JESD204) SFI 5.1Up to 8 Channels HyperTransport 3.0Up to 8 Channels 6G Protocols PCI Express Gen 2 (x1, x2, x4, x8) HiGig2, CEI 6G (SR/LR), Interlaken, DDR-XAUI, SPAUI 6G basic (proprietary), 6G SerialLite II 6G CPRI/OBSAI Fibre Channel (FC1/FC2/FC4)

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7 Hard IP for PCI Express Benefits Pre-verified, complex IP cores  x8, x4, x2, x1 PCI Express Base rev 2.0 compliant core (includes rev 1.1) supporting a rootport and endport function  Integrated Transaction layer (TL), Data Link layer (DLL), physical interface/media access control (PHY/MAC), and transceivers  2.5 Gbps (Gen 1) and 5 Gbps (Gen 2) per lane  Supports a PIPE 2.0 compliant interface Device cost reduction  Fit designs in a smaller FPGA  Resource savings Up to 25K LEs (x8 Gen 2 configuration) Embedded memory buffers  Replay buffer  Receive buffer (per virtual channel) Power savings relative to soft IP core implementations Shorter design and compile times

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8 Stratix III/IV I/O Stratix III/IV I/O Performance Stratix III/IV FPGAs InterconnectPerformance DDR3 533 MHz/1,067 Mbps DDR2400 MHz/800 Mbps QDR II350 MHz QDR II+400 MHz RLDRAM II400 MHz LVDS1.6 Gbps I/O feature Stratix III/IV FPGAs Benefit Dynamic on-chip termination Saves power DDR3 Read/Write leveling DIMM support Variable I/O delay Allows signal de-skew Up to 24 I/O banks distributed on all sides offer more flexibility

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9 TriMatrix Embedded Memory Optimized size for optimal memory/logic ratio and maximum memory bandwidth Dual-port RAM, error correction coding (ECC), low-power mode Memory functionsStratix IV devicesMemory Processor code storage Packet buffers External memory I/F cache Video frame buffers 16–64 M144K (2,048 x 72 bits) 600 MHz General purpose memory 462-1,280 M9K (256 x 36 bits) 600 MHz Shift registers Small FIFO buffers Filter delay lines 50 percent of the logic can be turned into an MLAB 600 MHz 9K Bits 144K Bits 640 Bits M144K MLAB M9K

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10 2 speed grade advantage with Stratix III/IV FPGAs saves power and cost Fast Medium Relative FPGA core performance % Slow 2 speed grade advantage Altera: Stratix III/IV FPGAs Xilinx: Virtex-5 FPGAs 1.80 Highest Performance on Stratix III/IV FPGAs

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11 Save Multiple Watts/Device (200K LEs) Note: Total power is based on 60 percent logic (ALUTs and FFs) at 200 MHz, 25 percent memory utilization of each type of memory, 50 percent DSP 18 x 18 block, 64in/64out 1.8-V LVCMOS (200 MHz), 128in/128out 2.5-V LVCMOS (200 MHz), 32in/32out (LVDS at 800 MHz), and 72-pin DDR3 interface power savings Stratix III, 1.1V EP3SL200 Stratix III, 0.9V EP3SL200 Stratix IV, 0.9V EP4SE230 Virtex-5, 1.0V V5-LX220 Power (W) Reduce power consumption— 50% with Stratix IV FPGAS 75% with HardCopy IV ASICs HardCopy IV, 0.9V HC230 29% 45% 50% 75% Devices

© 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12 Stratix IV GX Device Rollout Schedule The EAP is Altera’s Early Access Program for selected customers and projects. Engineering sample (ES) devices are RoHS-compliant by default (leaded ES package by special request). All packages will go to production with both leaded and RoHS- compliant options. DeviceEAPESProduction EP4SGX230December 2008February 2009June 2009 EP4SGX530March 2009April 2009August 2009 EP4SGX360NAAugust 2009October 2009 EP4SGX290NAAugust 2009October 2009 EP4SGX110NASeptember 2009 EP4SGX70NASeptember 2009