1 IT R&D Global Leader 고속 비디오 데이터 전송용 SerDes SoC ( 기술이전 ) 고속 비디오 데이터 전송용 SerDes SoC ( 기술이전 ) 융합부품소재연구부문 시스템반도체연구부 디지털 RF SoC 연구팀 책임연구원 박 문 양

2 목표 및 내용 ( 개발 목표 )  600Mbps ~ 3.75Gbps data rate 비디오 데이터 전송용 송, 수신 SoC 개발 - 600Mbps ~ 3.75Gbps SerDes 입출력 CDR SoC - 600Mbps ~ 3.75Gbps SerDes 입출력 PLL SoC * V-by-One Standard (Thine) LCD PANEL TCON CDR RX w/EQ SHIFT REG DATA LATCH DAC OUTPUT AMP PLL TX w/PE Rx DLL Column D-ICs HOST DATA PATH TIMING GEN VCO CFG REG I2C …… PMIC LED Driver BoostBuck R - C/PPWM GEN Protection Ref. Bias Channel ( 8 Ch ) Current Regulator PWM GEN Fault Detector S/R Display Panel Display I/F Wide-band PLL Wide-band CDR

3 목표 및 내용 ( 개발 목표 기술 수준 ) 기술개발 Item 목표 기술 수준 o 600Mbps ~ 3.75Gbps CDR with SerDes um CMOS technology (1.2 V and 3.3 V) Mb/s ~ 3.75 Gb/s Data Link Rate ( 세계 최고수준 ) - S2P De-serializes 1-bit serial data stream to 10-bit rate seamlessly - No external frequency reference - RMS jitter under quite supply : J RMS < 10ps - Jitter tolerance & Jitter transfer : Satisfies OC-192 spec. 0.3UI) - Input Eye mask of CDR (TBD) - Power consumption of CDR & S2P(core) : < 100mW o 600Mbps ~ 3.75Gbps PLL with SerDes um CMOS technology (1.2 V and 3.3 V) Mb/s ~ 3.75 Gb/s Data Link Rate ( 세계 최고수준 ) - P2S serializes 10bit data stream from formatter to 1-bit data - 20MHz ~100MHz Tx Reference frequency - Peak to peak jitter under quite supply : J PP < 30ps - Power consumption of PLL(core) : < 10mW

4 SerDes CDR 개발 SerDes CDR specification SerDes CDR 구조 Rx1 Chip photo (Chip size : 2.2mm X 2.2mm) Rx 1 and 2 Package (2 종 ) (56 and 28 Lead QFN) Contents Amount (Measurement) Description Process0.13um CMOSUMC 130nm process Supply voltage 1.2V (1.2V) 1.2V Input data rate 600Mbps ~ 3.75Gbps (500Mbps ~ 5.6Gbps) Input data rate to SerDes PLL Output data rate Deserialized 10 bits 60Mbps ~ 375Mbps (50Mbps ~560Mbps) Recovered Clock 을 이용한 Output data rate Output clock frequency 60MHz~375MHz (50MHz ~560MHz) RXCLK Frequency JRMS 10ps (6ps) RMS jitter under quiet Power consumption < 40-mW ( 31.2 mW) PLL & Serializer & CML

5 SerDes PLL 개발 CLK_INPUT Divider ratio by Color depth VCO_out [9:0] Frequency Tx_out Data rate 20MHz ~75MHz 6/8/10120MHz ~ 750MHz 600Mbps ~ 3.75Gbps Contents Amount (Measurement) Description Process0.13um CMOSUMC 130nm process Supply voltage 1.2V FCLKREF 20M ~ 100MHz (20M ~ 100MHz) PLL input reference frequency TX_OUT 600M~3.75Gbps (600M~3.75Gbps) TX output data rate JRMS 5ps (4.4ps) RMS jitter under quiet TX Clock 300MHz ~ 1.875GHz (300MHz ~ 1.875GHz) Tx Clock frequency Power consumption < 60-mW **** ( 68 mW) PLL & Serializer & CML SerDes PLL specification SerDes PLL 구조 TX1 Chip photo (Chip size : 2.2mm X 2.2mm) TX1 Package (56 Lead QFN)

6 SerDes CDR 시험 결과 500Mbps 5.6Gbps Jitter histogram Waveforms of recovered data and clock

7 SerDes PLL 시험 결과 Eye pattern : PRBS data 600Mbps 3.75Gbps Eye Diagram 에서 Tx 클럭 (1.875GHz) 에서 RMS Jitter Histogram 에서 Tx 클럭 (1.875GHz) 에서 RMS Jitter 1.875GHz

8 SerDes PLL & CDR 연동 시험 결과 Error Detector (MP1764C: ~12.5Gbps) Input : Internal PRBS Data PRBS data length : 155 TX Board RX Board Setting of PRBS data with 155-data length SMA Connector It was verified by measurement !!