Status of CRU FW Resource Estimations Erno DAVID Wigner Research Center for Physics (HU) 10 March, 2016

2 CRU FW Resource Usage Investigation Status (1) (History) April 2015: First CC design (x48 GBT links, 1920 FIFOs, dual x8 PCIe DMA) Result – The design can be fitted into Arria 10, but it was based on a now obsolete code base July 2015 (1 st CRU Workshop): The new Arria 10 GBT-FPGA port become available Decision to rebuild the CC design and develop a more accurate “dummy cluster finder” logic with the TPC team November 2015: First release of the core CRU framework with x24 GBT links, x1 TTS link, x2 PCIe x8, the User Logic part contains just a skeleton (there is no dummy CF inside) January 2016: The TPC switched to RAW SAMPA readout mode -> need for 40 GBT incoming links It become evident that the initial GBT-FPGA resource usage numbers were unrealistic It has been fixed in a standalone design February 2016: We started to extend the CRU framework with x24/x36/x48 GBT Links March 2016: The TPC switched to 5 MHz RAW SAMPA readout mode -> need for 20 GBT incoming links

3 CRU FW Resource Usage Investigation Status (2) (Our Aims) Our aims / questions? 1 - Provide reliable resource usage numbers about core CRU framework (mainly GBT + PCIe) The answer will be the used: ALMs, FFs, PLLs, XCVRs, M20Ks 2 - Is it possible to implement the core CRU firmware with 24/36/48 bidir GBT Links The answer will be YES or NO 3 - Investigate further optimizations for the TPC Only 20 GBT Tx, Only 20/40 GBT Rx, only 120 MHz, fewer PLLs Implement large number of latency optimized GBT-FPGA RX channels

4 CRU Resource Usage Investigation Status (3) (Current Status and Next Steps) Current status? 1 - Reliable resource usage numbers We can take Jubin’s numbers as a good approximation, it has been repeated and looks stable After integration we can get more relevant numbers 2 - Core CRU firmware with 24/36/48 bidir GBT Links The git repository modification for 24/36/48 links is done -> OK for 24 GBT But the 36/48 version is fails due to the “clock problems” – needs the fix from Jubin to say YES 3 - Investigate further optimizations for the TPC Only 20 GBT Tx, Only 20/40 GBT Rx, 120 MHz, fewer PLLs – Some promising simulations Original port 24/36/48 GBT (Jubin) Git repository 24 GBT (Erno) Modified git repository 24/36/48 GBT (Erno) Fixed original port with new architecture 24/36/48 GBT (Jubin) Fixed git repository 24/36/48 GBT (Erno) x Modified git repository 120MHz 24/36/48 GBT (Erno)