Murali Venkatasubramanian Vishwani D. Agrawal Ph.D. Candidate James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University.

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Presentation transcript:

Murali Venkatasubramanian Vishwani D. Agrawal Ph.D. Candidate James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

 Definition of problem statement  Research summary of ATPG  Overview of proposed algorithm  Analysis of results  Elaboration of Future work  Conclusion May 10, 20162North Atlantic Test Workshop 2016

 Given a stuck-at fault, find a test.  Specifically, finding tests for hard to detect stuck-at faults.  Rephrase the VLSI Testing problem as a database search problem.  Need for research to harness potential of database search.  Application of quantum search towards test generation.  Improve the bottleneck of finding the unique tests. May 10, 20163North Atlantic Test Workshop 2016

May 10,  Fault detection problem is NP complete [Ibarra and Sahni, 1975; Fujiwara and Toida, 1982; Seroussi and Bshouty, 1988].  Worst-case computational complexity is an exponential function in circuit size.  Nature of NP problem.  Generation of test vectors a classic VLSI problem.  Tackled by numerous algorithms. North Atlantic Test Workshop 2016

May 10,  Deterministic algorithms derived from structural description of circuits.  D Algorithm [Roth, 1966].  PODEM [Goel, 1981].  FAN [Fujiwara and Shimono, 1983].  And various others...  Test sets derived from functional description of circuits [Akers, 1972; Reddy, 1973].  Use of weighted random test generators.  Heuristics like input switching activity and weight assignment [Schnurmann et al., 1972].  Skewing input probabiltiy to attain maximum output entropy [Agrawal, 1981].  Adaptive test generation  Genetic algorithms [Saab et al. 1992; O’Dare and Arslan, 1994; Corno et al., 1996].  Anti-random test generators [Malaiya, 1995].  Using spectral properties of successful tests to generate new test vectors [Yogi and Agrawal, 2006]. North Atlantic Test Workshop 2016

 Current algorithms hit a bottleneck when testing hard- to-detect faults.  Because we are testing hard-to-detect faults, we generally have many trial vectors that do not work.  All known algorithms use previous successes to generate new test vectors.  But, test generation has lots more failed attempts than successful ones.  Current algorithms ignoring a lot of potentially valuable information.  How to design a new test algorithm which utilizes the information from failed attempts effectively? May 10, 20167North Atlantic Test Workshop 2016

 How does one prosper in life??  Repeating steps from previous successes. ▪ As people say, do not change a successful formula.  Learning from past failures and avoiding them.  Main conjecture is to avoid all vectors with properties similar to known failed test vectors.  The direction of search gets skewed towards the correct test vector.  Proposed algorithm utilizes both successful and failed test vectors.  Moving away from failed vectors will lead to solution in quicker iterations. May 10, 20169North Atlantic Test Workshop 2016

 Growing interest in quantum computing leading to revisiting of NP hard problems.  Find optimal solutions in linear time.  A n primary input (PI) circuit can have N = 2 n possible test vector combinations.  A test can be found from among these N vectors.  Hence, VLSI testing problem can rephrased as an unsorted database search problem of N elements.  In our best interest to implement one of the fastest unsorted database search algorithms to find test vectors.  Grover's quantum search algorithm [Grover, 1996] can search through an unsorted database in sub-linear time.  Deemed the fastest way to search an unsorted database theoretically [Bennett el al., 1997]. May 10, North Atlantic Test Workshop 2016

 Current algorithms hit a bottleneck when testing hard-to-detect faults.  Because we are testing hard-to-detect faults, we generally have many trial vectors that do not work.  Main conjecture is to avoid all vectors with properties similar to known failed test vectors.  The direction of search gets skewed towards the correct test vector.  Proposed algorithm utilizes both successful and failed test vectors.  Moving away from failed vectors will lead to solution in quicker iterations.  Test vectors in the vector space are classified into three categories:  Activation vectors  Propagation vectors  Failed vectors May 10, North Atlantic Test Workshop 2016

May 10, North Atlantic Test Workshop 2016 Classification of vectors in three categories for stuck-at fault [Venkatasubramanian and Agrawal, 2015].

May 10, North Atlantic Test Workshop 2016  Initialize weighted probabilities of all PIs being bit "1" to 0.5 and extract a vector.  Add test vector to the failed vector list and recalculate weighted probabilities of all PIs.  Invert the weighted probability and extract a bit value from the new calculated probability.  Operation performed till an activation or propagation vector is extracted.

May 10, North Atlantic Test Workshop 2016  Derive new vectors using weights which extracted previous activation/propagation vector.  Tweak the weights in smaller increments utilizing the failed vector weights for direction.  Idea is move towards the intersection of activation and propagation vectors when inside "region of desirability".  Avoid going back to failed vector region.

May 10, Initial probability values for random search Initial Probability values for proposed algorithm North Atlantic Test Workshop 2016

May 10, Probability values for random search Probability values for proposed algorithm North Atlantic Test Workshop 2016

May 10, Probability values for random search Probability values for proposed algorithm North Atlantic Test Workshop 2016

May 10, Probability values for random search Probability values for proposed algorithm North Atlantic Test Workshop 2016

 The given circuit has a stuck-at-1 fault on a line.  Fault site has:  One successful test.  Eight activation vectors.  Four propagation vectors.  Performed 100 trial runs on the faulty circuit. May 10, North Atlantic Test Workshop 2016

May 10, Iterative search duration distribution to search for the correct test vector. North Atlantic Test Workshop 2016

May 10, Circuit Search space size, N = 2 #PI Grover’s quantum search (√N) Proposed algorithm Random search (~ N/2) Test circuit (#PI = 6) ALU control (#PI = 7) Decoder (#PI = 8) Ones Counter (#PI = 9) CAVL coder (#PI = 10) North Atlantic Test Workshop 2016

May 10, Iterative search duration distribution to search for the correct test vector. North Atlantic Test Workshop 2016

May 10, Iterative search duration distribution to search for the correct test vector. North Atlantic Test Workshop 2016

May 10, Iterative search duration distribution to search for the correct test vector. North Atlantic Test Workshop 2016

May 10, Iterative search duration distribution to search for the correct test vector. North Atlantic Test Workshop 2016

May 10, North Atlantic Test Workshop 2016 Test vector search complexity: Average search iterations versus no. of primary inputs

 Use “Mahalanobis distance” to formalize algorithm [Mahalanobis, 1936].  Measure of distance of P from a deviation D.  Optimizing the algorithm for more efficiency.  Try different methods of implementation e.g., consider correlation among bits of a vector.  Running simulations on all larger benchmark circuits. May 10, North Atlantic Test Workshop 2016

 Showed evolution of ATPG algorithms over the past 50 years.  Redefined the testing problem as a database search problem.  Results demonstrate proof of concept of our algorithm.  Comparison with quantum search shows algorithm is on same order of search time or iteration time. May 10, North Atlantic Test Workshop 2016

Success consists of going from failure to failure without loss of enthusiasm. - Sir Winston Churchill May 10, North Atlantic Test Workshop 2016

[1] O. H. Ibarra and S. Sahni, “Polynomially complete fault detection problems,” IEEE Trans. Computers, vol. 24, no. 3, pp. 242–249, [2] H. Fujiwara and S. Toida, “The complexity of fault detection problems for combinational logic circuits,” IEEE Transactions on Computers, vol. 100, no. 6, pp. 555–560, [3] G. Seroussi and N. H. Bshouty, “Vector sets for exhaustive testing of logic circuits,” IEEE Transactions on Information Theory, vol. 34, no. 3, pp. 513–522, [4] J. P. Roth, “Diagnosis of automata failures: A calculus and a method,” IBM Journal of Research and Development, vol. 10, no. 4, pp. 278–291, [5] P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Transactions on Computers, vol. 100, no. 3, pp. 215–222, [6] H. Fujiwara and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Transactions on Computers, vol. 100, no. 12, pp. 1137–1144, [7] S. B. Akers, “Universal test sets for logic networks,” IEEE Conference Record of 13th Annual Symposium on Switching and Automata Theory, 1972, pp. 177–184. [8] S. M. Reddy, “Complete test sets for logic functions,” IEEE Transactions on Computers, vol. 100, no. 11, pp. 1016–1020, May 10, North Atlantic Test Workshop 2016

[9] H. D. Schnurmann, E. Lindbloom, and R. G. Carpenter, “The weighted random test- pattern generator,” IEEE Transactions on Computers, vol. 100, no. 7, pp. 695–700, [10] V. D. Agrawal, “An information theoretic approach to digital fault testing,” IEEE Transactions on Computers, vol. 30, no. 8, pp. 582–587, [11] D. G. Saab, Y. G. Saab, and J. A. Abraham, “CRIS: A Test Cultivation Program for Sequential VLSI Circuits,” in Proc. IEEE/ACM International Conference on Computer- Aided Design, 1992, pp. 216–219. [12] M. O’Dare and T. Arslan, “Generating Test Patterns for VLSI Circuits Using a Genetic Algorithm,” Electronics Letters, vol. 30, no. 10, pp. 778–779, [13] F. Corno, P. Prinetto, M. Rebaudengo, and M. S. Reorda, “GATTO: A Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 991–1000, [14] Y. K. Malaiya, “Antirandom Testing: Getting The Most Out of Black-box Testing,” in Proc. 6th IEEE International Symp. Software Reliability Engineering, 1995, pp. 86–95. [15] N. Yogi and V. D. Agrawal, “Spectral RTL test generation for gate-level stuck-at faults,” Proc. 15 th IEEE Asian Test Symposium, 2006, pp. 83–88. May 10, North Atlantic Test Workshop 2016

[16] S. T. Chakradhar, V. D. Agrawal, and S. G. Rothweiler, “A Transitive Closure Algorithm for Test Generation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 7, pp. 1015–1028, [17] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation,” in Proc. 9th IEEE Great Lakes Symp. VLSI, 1999, pp. 24–27. [18] P. Venkataramani, S. Sindia, and V. D. Agrawal, “A Test Time Theorem and its Applications,” Journal of Electronic Testing: Theory and Applications, vol. 30, no. 2, pp. 229–236, [19] V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Power-aware SoC Test Optimization Through Dynamic Voltage and Frequency Scaling,” in Proc. IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 2013, pp. 102–107. [20] R. Drechsler, S. Eggersgluβ, G. Fey, A. Glowatz, F. Hapke, J. Schloeffel, and D. Tille, “On Acceleration of SAT-Based ATPG for Industrial Designs,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 27, no. 7, pp. 1329–1333, July [21] S. Kirkpatrick, C. D. Gelatt, M. P. Vecchi, et al., “Optimization by Simulated Annealing,” Science, vol. 220, no. 4598, pp. 671– 680, May 10, North Atlantic Test Workshop 2016

[22] P. W. Shor, “Polynomial-time Algorithms For Prime Factorization and Discrete Logarithms on a Quantum Computer,” SIAM Journal on Computing, vol. 26, no. 5, pp. 1484– 1509, [23] L. K. Grover, “A Fast Quantum Mechanical Algorithm for Database Search,” in Proc. 28th Annual ACM Symposium on Theory of Computing, 1996, pp. 212–219. [24] M. A. Nielsen and I. L. Chuang, Quantum Computation and Quantum Information. New York: Cambridge University Press, 10th edition, [25]P. C. Mahalanobis, “On the Generalized Distance in Statistics,” Proceedings of the National Institute of Sciences (Calcutta), vol. 2, pp. 49–55, [25] M. Venkatasubramanian and V. D. Agrawal, “Quest for a Quantum Search Algorithm for Testing Stuck-at Faults in Digital Circuits,” in Proc. 29th IEEE International Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 127–132, Oct [26] M. Venkatasubramanian and V. Agrawal, “Database Search and ATPG – Interdisciplinary Domains and Algorithms,” in 29th IEEE International Conference on VLSI Design, Jan [27] M. Venkatasubramanian and V. Agrawal, “A New Test Vector Search Algorithm for a Single Stuck-at Fault using Probabilistic Correlation,” in IEEE 23 rd North Atlantic Test Workshop (NATW), pp. 57 – 60, May May 10, North Atlantic Test Workshop 2016