GPL Board Pattern Generator for the Level-0 Decision Unit Hervé Chanal, Rémi Cornat, Emmanuel Delage, Olivier Deschamps, Julien Laubser, Jacques Lecoq, Magali Magne, Pascal Perret PRR – July,

GPL Functionalities L0DU test bench GPL Board Test modes GPL Design Block diagram Clock network Spectra Quest study Test Outline

Test bench for L0DU L0DU algorithms Simulates L0 sub-trigger outputs : CALO, MUON and PileUp systems Simulates some experimental problems Erroneous data, transmission errors… Characterize the links Allows to test the optical links and the RS link External test bench Will be in the L0DU rack in the LHCb pit Will be in our laboratory Board Purpose

Part I The GPL Functionalities

L0DU Test Bench GPLL0DU Optical links (2 MPO Ribbons) L0DU Decision (RSDA word) USB PVSS CCPC Ethernet DIM ECS TEST BENCH SLOW CONTROL TTC

GPL Board PCB: 16 layers VME 9U 2 optical channels x 12 independent outputs 1 optical input Input: RS output from L0DU 3 FPGA 12 External memories TTC mezzanine Interface: - USB - ECS from L0DU Channel A Channel B TTC Readout Sup. L0DU Input Opt. Input Usb interface

Board Properties Power supply input : 5 V, 3.3 V, 2.5 V TELL1 back plane External 24 optical transmitter channels Clock inputs : - TTCrq - 80 MHz LHC quartz 2 clock distribution networks Channel A (FPGA 2) FPGA 1 / Channel B (FPGA 3) with delay skew and QPLL

L0DU Test Bench GPL L0DU mezzanine

Test Modes (1/2) On each 16 bits optical output An identification word A counter The RAM content (128k / output) 18 LHC cycles Add IDLE characters between each cycle Add delays between each outputs Change the clock phases between the two channels Two clock networks

Test Modes (2/2) On each 16 bit input (Opt. input and L0DU decision) Store the incoming data in a RAM (32k) Compare the incoming counter with a local one 16 bits error counter / 48 bits word counter Start signal for sending data or data acquisition Software / Push button Bunch Count Reset (Synchronisation with L0DU)

Part II GPL Design

Block Diagram Processing FPGA 2 Processing FPGA 3 Control FPGA 1

Clock Network

TLK Serializer Clock Jitter TLK clock input Very sensitive Jitter in the specification ? Yes Measure 2 clock networks !

Spectra Quest Study Complex design, high wire density, complex clock network Board simulation Cross talk, wave reflexion, wire impedance Tested parts Links between the FPGA(2 or3) and the TLK2501 High wire density Links between the FPGA Wire Length Links between the FPGA and the memories Address bus tree Links between the HFBR772 and the TLK2501 High frequency HFBR772 6 RAM 12 * TLK 2501 FPGA

Spectra Quest Study PCB Links between a FPGA and the TLK

GPL tests GPL board

Optical Output Power Measured with a photometer 24 links With/Without attenuator → In the constructor margins First HFBR772 (Channel A) fiber n°= A0A1A2A3A4A5A6A7A8A9A10A11 color of the fiber blueorangegreenbrowngreywhiteredblackyellowpurplepinkaqua Pt1dBm Second HFBR772 (Channel B) fiber n°= B0B1B2B3B4B5B6B7B8B9B10B11 color of the fiber blueorangegreenbrowngreywhiteredblackyellowpurplepinkaqua Pt1dBm

Status Design started : August 2005 GPL board received: 25/01/2006 PCB tests Electrical test with the TTC clock network Sending test through the 24 channels Optical receiver USB interface External memories VHDL : almost finished To do : ECS access + Opt. input Software 

Conclusion GPL board is fully operational ! Used to test the links Will be used to test the complete dataflow and for the commissioning