UniBoard Meeting,October 12-13th 2010 Jonathan Hargreaves, JIVE Eric Kooistra, ASTRON UniBoard Testing UniBoard Meeting, October12-13 th 2010 Contract no

UniBoard Meeting,October 12-13th 2010 The Tests FPGA with Nios II uP and JTAG UART Transceivers 10GbE 10/100/ 1GbE DDR3memory ADC clock,pps,wdi ID,test IO I 2 C,SPI,MDIO JTAG Terminal Configuration flash Test each interface separately to verify the board Then test everything at once

UniBoard Meeting,October 12-13th 2010 DDR Memory Testing Write and read back pseudo random patterns in sequential and data mask modes Test exercises each address line Test can be run in single shot or continuous modes Tested 1GB and 4GB modules at 800MT/s and 1066MT/s (+20%) Test can fail immediately because the module was not initialised correctly Module was not seated correctly or wrong module inserted Power supply failure (1.5V) Test starts but one or more read/write accesses gives an error Can be due to a single data, address or control line Further testing by toggling the outputs and using JTAG revealed 4 bad connections on the board

UniBoard Meeting,October 12-13th 2010 Testing the FN 10Gbps ports EPCS was switched on Tested 1m and 10m optical cable and SFP+ modules from JDSU and Finisar Port 3 not tested due to RX-TX swap ARP and UDP packets transmitted while monitoring error counts in the PHY chip Also test 2m and 5m passive copper (Direct Attach) and 2m active copper cables XAUI and MDIO connections between FPGA and PHY chip were OK MDIO XAUI FPGA Altera GX230 PHY VSC SFP+ Cage TYCO MDIO XAUI FPGA Altera GX230 PHY VSC SFP+ Cage TYCO Cable Under Test

UniBoard Meeting,October 12-13th 2010 Testing the FN 10Gbps ports All 3 ports worked well with 10m optical Port 2 struggled with 1m optical Active copper cable gave high errors 2m passive copper was OK on ports 0 and 1 but not 2 SFP+ is essentially analogue end to end May need to optimise TX gain, pre- emphasis, de-emphasis and RX equalisation each link Optical measurements, 1m & 10m multimode cables, rx equalization setting x1, Extended PCS on PortCableLink E-PCS corrected/uncorrected errors per second (typical) Length of run (hrs) Block errors Character errors Sequenc e errors BER based on char err 01mFN0 -> FN10/ FN1 -> FN00/ mFN0 -> FN10/ FN1 -> FN00/ mFN2 -> FN31/ FN3 -> FN21/ mFN2 -> FN30/ FN3 -> FN20/ mFN0 -> FN10/ FN1 -> FN00/ mFN0 -> FN11/ FN1 -> FN00/ mFN2 -> FN31/ FN3 -> FN20/ mFN2 -> FN30/ FN3 -> FN20/ mFN0 -> FN10/ FN1 -> FN00x748/ E-12 10mFN0 -> FN10/ FN1 -> FN00 to 3/ mFN2 -> FN30x234/ E-12 FN3 -> FN20x144/ E-13 10mFN2 -> FN30x3 to 0xb/ FN3 -> FN20/

UniBoard Meeting,October 12-13th 2010 Testing the BN 10Gbps ports The BN XAUI connections were tested using the XGB board and CX4 cables between 1m and 5m in length The status of the transmit and receive PLLs was checked to make sure they stayed locked during the test Ports 0 1 and 2 transmitted ARP and UDP packets to their neighbours

UniBoard Meeting,October 12-13th 2010 The Tests - continued FPGA with Nios II uP and JTAG UART Transceivers 10GbE 10/100/ 1GbE DDR3memory ADC clock,pps,wdi ID,test IO I 2 C,SPI,MDIO JTAG Terminal Configuration flash

On board transceivers FN-BN mesh Tested the 12 full featured transceivers The 4 CMU transceivers have not been tested, because the 12 suffice 16 hours test for 8 FPGA with 12 TR each at Gbps went OK

On board transceivers FN-BN mesh – 8 terminals

BN-BI transceiver port test Uses the 12 full featured transceivers The 4 CMU transceivers have not been tested, because the 12 suffice 15 hours test at 5 Gbps for all BN with 6 CX4 cables upto 5 m went OK A test using XAUI on all TR including the CMU TR also went OK.

BN-ADC port test Test using 4 LOFAR receiver units per BN Each receiver unit delivers 8 bit counter data at 200 Msps via LVDS All 4 BN received the counter data from the receiver units OK. The I2C connections between BN and receiver units function OK. Higher sample rate tests will be done when the APERTIF ADC unit is available.

1 Gb Ethernet Test Test whereby the 8 nodes transmit > 1000 frames to each other via the on board 1 GbE switch went OK. Communication between 8 nodes and the 4 RJ45 connectors still under test.

Auxiliary tests WDI (watchdog interrupt) works OK. INTA, INTB pull up lines between FPGAs work OK. I2C to on board sensors - FPGA temperature sensors for all 8 nodes: OK - 1GbE switch temperature sensor via BN3: ? - Hot swap controller voltage sensor via BN3: ?

Good to know (see UniBoard SVN for more) Development scripts: - unb_sopc  generate SOPC system files - unb_app  compile SW - unb_qcomp  synthesize the design - unb_sof  load image on FPGA(s) - unb_rld  compile SW and download to FPGA Unb_common: - FPGA pinning TCL files - unb_node_ctrl.vhd  FPGA clock, reset, watchdog - unb_system_info.vhd  FPGA ID, version, g_sim - SW function PIO debug wave  track SW in Wave window Generic g_sim to distinguish between target and simulation without editing the VHDL file FPGA node reservation web page

UniBoard reservation web page

To do: integrated test design Test all interfaces in one design for efficient functional verification of the next 8 UniBoards Full load test using dummy logic, RAM and DSP to heat the FPGA and verify the power supplies