Pixel detector/Readout for SuperB T.Kawasaki Niigata-U

Introduction Baseline for Super B VXD –To improve IP resolution(1/2-1/3 of present) Pixel detector is necessary Smaller-radius beampip  Rbp = 1cm Good intrinsic resolution  50um or less Smaller amount of material  need studies The space for Pixel detector are constrained by Strip detector configuration. Based on Hazumi’s proposal –3 or 5 DSSD layer with r > 3cm –2 pixel layers with 1.2<r<3cm Proposal at 2 nd workshop, Jan 2002

Rbp = 1cm 2layer Pixel 4~5layer DSSDs Rcdc > 15cm Configuration of SuperB VXD 15cm Pixel DSSD w/ Pipeline readout Additional DSSD layers CDC

Requirement for Pixel Detector Granularity <100×50μm to cope with occupancy –Not from resolution requirement –Can be loosen with shorter shaping time(Tp) Radiation hardness >5Mrad/year Fast readout (<100usec?) σpt ～ 5μm to improve resolution by factor 2 Low material budget in order not to spoil the resolution –For Calorimetry and tracking EoI Based on these requirement, making first conceptual design

Pixel detector option Option (only silicon material) –CCD ⇒ slow, radiation, cooling –Monolithic Active Pixel ⇒ not established yet? Best solution (Ref. H.Palka’s –Hybrid ⇒ most popular Matured for ATLAS, CMS, ALICE…. –Other challenging options… Our requirement –Similar to LHC ⇒ rad tolerant, high rate, high occupancy –Except material budget –LHC groups have 10years experience. As most feasible solution for 2006 start –Hybrid pixel detector

Typical silicon pixel detector system (hybrid pixel case) Pixel and sensor size is limited by FE size and bonding pitch Put FE chip on pixel sensor –2,000 ～ 10,000 input pads –Include pipeline –Trig a few kHz –Fast shaping signal(20-50ns) Control chip on hybrid –FIFO –Trig a few 100 Hz Decoder Optical link Gb/module/s CMS pixel module Detector design is constraint by readout scheme(chip design) Command to control chip Control FE Signal driver Local bus Data FE chip sensor Local bus Support &cooling Online Farm Sparsification Backend in EH

Pixel Detector design for super B Things to be established –Sensor ⇒ design, Rad-hardness –FE Chip Difficult to develop original chip…(need >5 year) –Chip-sensor bonding (bump?) –Control chip development –Cooling, mechanical support, material. Etc.. Assuming Typical FE chip size is 1×1cm R=13mm 15<theta<155 deg. Difficult to make 2 kinds of sensor ⇒ In total=128chips=150cm^2 1cm 13mm 80mm Pixel sensor=40×10mm^2 Control chip Support&local bus FE chip

Data size estimation Occupancy – ～ 1% (50×100um^2 with Tp=1us, r=1cm) Data size (assuming 150cm^2 detector area) –Sparsification on “control chip” or/and “backend electronics” –50×100um^2 ⇒ 3M pixel ⇒ ×1% ⇒ 4kB/event for Binary data – 30kB/event for 8 bit Analog data –+ 90kB pixel position data!! (3Byte/pixel. compress?) Full address is not necessary for each pixel.. Data size and occupancy can be reduced by shorter shaping time!! –We can loosen granularity of pixel size ⇒ Less data size ⇒ Degrade intrinsic resolution (need simulation study!! )

Requirement on readout latency Trigger Rate for 10^35cm^-2s^-1 expect. design Background2kHz 5kHz Physics1kHz 1kHz Datasize100kB 100kB L1 Data flow300MB/s 600MB/s At storage150MB/s 225MB/s ~10usec/event for 5% 5kHz trigger rate ⇒ (10KHz trigger? More hard!) Need these functions inside FE/Control chip/Backend Multi level trigger (L0 scheme?) Pipeline memory(use L1.5 trigger?) Sparsification EoI Readout latency depend on; –#Pixel in 1 FE chip ⇒ FE chip selection ⇒ Consider FE Chip candidates

CMS (pixel vtx detector ) Analog readout 40MHz function Pixel size =150×150um 52×53=2,756 pads Tp=50ns 8 time stamps FIFO on peripheral part Readout time –Readout of 1 pixel needs 6 clks(150ns) –Depend on occupancy( ～ 0.2%) –<1us/FE chip? Good for us (if it works) No hopeful results are seen as of now

ALICE(VTX)/BTeV(RICH) Binary readout Tp =25 ns 2 delays for L1 trig with 5us latency –8bit counter (up to 25.6 us delay) 4 depth FIFO for L2 trig with 100us 10MHz (40MHz for BTeV version) Pixel size=50×400um^2, – 32columns×256rows= 8,192 –25.6us/FE chip Will be thinned to 150um Fast OR Trigger :diagnostic purpose Most feasible solution as of now Ref Ohnishi’s 2002 We are making contact 256rows 32columns Peripheral part 32bit data

How to use for Super Belle? If we employ ALICE chip –Readout latency =25.6us/FE chip 13% trigger (4 chips should be paralleled) –Occupancy decreased ⇒ thanks to Tp=25ns (even the pixel size is 4times larger.1/5 of first estimation) Problem –Material budget Sensor(300um)+chip(300um) +FLEX bus /layer –Thinning technique will be performed for sensor and chip( to 150um) –X/X0 =1.5%(present) ⇒ 1% Cooling 0.6% –Intrinsic resolution 50×400um^2, binary. ⇒ enough for us? Need simulation study Need to introduce Multi level trigger (next slide)

Multi level trigger for ALICE chip Trig 1 Trig 2 ALICE L1: 5us L2: <100us Single Trig L0: 0.5us L1:2us Multi Trig L1: 2us (10kHz) L1.5 Trig1 Trig2 Single pixel rate =600Hz (150ns window, 50×400um) Within 400us(100us×4 depth FIFO) 1kHz(phys.) ⇒ 2.56% dead time!!

Summary 1 st conceptual design of Belle Pixel detector Most feasible solution –Hybrid pixel with LHC technique –Detector configuration 150cm^2 area –Introducing ALICE pixel detector chip Need L1.5 trigger within 400us(1kHz) Readout latency = 25.6us (or 102us) 2.6% dead (or 10.2%) Data size= ( 4kB + 90kB(?) position data)/5 Is Resolution enough (50×400um^2)? –Need simulation study

Idea 1 Crosstype Super layer structure –Common Cooling ⇒ less material Use 50×400um pixel for phi and z Problem –Layer should be divided to small sensors due to peripheral part Peripheral part

Idea 2 Multi-layer FLEX –Sandwich multi-layer FLEX(or extract signal line to chip put outside acceptance) –Gang some apart pixels (solve by strip sensor information) –More precise sensor can be used –Occupancy increase are allowed with the relaxed requirement by shorter Tp FLEX –Line pitch is limited >25um –How many layers FLEX can be achieved? FE Pad Pixel Example : 1 to 4 for 4 pad case FLEX

Summary(design)

Backup slides