LECC2003: The 96 Chann FED Tester: Greg Iles30 September The 96 channel FED Tester Outline: (1) Background (2) Requirements of the FED Tester (3) The FED Tester design (4) Data recorded by FED (5) Conclusions & current status FED Tester FED

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Microstrip Tracker readout chain –10 million detector channels –100,000 APV25 readout chips in the tracker –Analogue readout –50,000 optical readout links –Optical links transmit equivalent to kHz trigger rate –500 Front End Drivers (FEDs)

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Front End Driver (FED) 96 optical fibres inputs, each from a multiplexed pair of APVs 8 front end blocks each driven by a 12 way optical ribbon cable Raw input data rate (all 96 fibres) = 3.4GB/s. Output rate down s-link = 50MB/s /% occupancy VMEData processing FPGA Power S-Link System FPGA FE Unit

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Front End (FE) Unit on FED Opto-RX, 12 way 12 x Buffers Delay FPGA (ADC clk timing) 6 x Dual 40MHz, 10bit ADCs A large FPGA (Virtex II, 1.5M gate) performs signal processing - common mode subtraction, - pedestal subtraction, - cluster finding, - sync checking Optical ribbon cable input For more information see ”The CMS Tracker Front End Driver”, J.Coughlan (RAL), Trigger Electronics, B2.8, Wednesday 15:15 Analogue circuitry duplicated on secondary side

LECC2003: The 96 Chann FED Tester: Greg Iles30 September FED continued... Production schedule –Preproduction batch mid 2004 –Full production in early 2005 –Installation and commissioning of system in mid 2005 Where do we need tester... –Development, production testing and possibly for system testing (i.e. integration of FED with other CMS components) Relatively sophisticated tester needed to evaluate FEDs fully –Need to compare analogue input with digital outputs Large volume of well defined data must be scrutinised –Analogue performance should not degrade system Noise - characterise complete FED, not just single channels Input data should be very stable - challenging given laser temperature sensitivity

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Requirements of FED Tester –Signals must mimic those from the APVs, yet allow flexibility for other tests –Drive 96 analogue optical channels –Use the Analogue Opto Hybrid (AOH) to convert from electrical to optical, just as in the CMS Tracker. 3 Channels per AOH 32 AOHs each with I2C interface Require temperature control because AOH temperature sensitive. Analogue Opto-Hybrid ADC sampling at 20MHzSignal magnitude Digital header 128 analogue values (one for each microstrip) MIP APV Data Frame

LECC2003: The 96 Chann FED Tester: Greg Iles30 September AOH temperature sensitivity –NOT a problem for Tracker because –(i) sensitivity reduces with temperature, –(ii) tracker temperature kept constant and –(iii) FED can apply common mode subtraction to data We measured worst case drift of ~ 0.5 MIPs per 30 °C

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Temperature control system –Temperature of AOHs controlled via Proportional, Integral, Differential (PID) algorithm in FPGA. Heater The FPGA loops over all 8 AOH temp control systems every second (a) AOH temperature read via I2C (b) Heating power calculated with PID algorithm and written back via I2C I2C bus AOH Thermometer ADC DAC = Thermal bridge x8 Integral term for steady state power Differential term damps system Proportional term

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Temperature stability –Prototypes show that we should be able to maintain temperature stability to +/ ‑ 0.2 ºC. –Requires laboratory temperature to remain stable to within +/ ‑ 3 ºC. –Must insulate AOH from FR4 substrate to reduce cooling. –Copper = 400 W/(m.K) –FR4 = 1.7 W/(m.K) –Perspex = 0.18 W/(m.K) Laboratory temp ~ 23ºC

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Overview of test system FED Tester Master In FED /12 VME Clock & Control Slave Out x 5 Slave In Opto x 24 Opto-Rx, 12 way Optical Other VME Backplane TTC S-link FED Tester Master In Slave Out x 5 Slave In Opto x 24 FED Tester Master In Slave Out x 5 Slave In Opto x 24 FED Tester Master In Slave Out x 5 Slave In Opto x 24 VME bus S-link to DAQ Optional /12 FED Tester and FED are both 9U VME cards

LECC2003: The 96 Chann FED Tester: Greg Iles30 September FED Tester design System control FPGA VME FPGA Temp Control AOH I2C VME to Wishbone bridge x-point switch network Multiplexed APV pair Trigger & Clock Control System Optical channel DAC, 12 bit Multiplexed APV pair Slow control Multiplexed APV pair QPLL Master In QPLL Slave In Slave Out VME Other AOH with temp ctrl Serial Wishbone link x24 AOH with temp ctrl 24 Optical Channels

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Prototype FED Tester DACs System FPGA VME FPGA AOHs x-point switch Power QPLLs Master & slave I/O Optical outputs Prototype FED Tester is populated with: 1 x 3channel AOHs 7 x 2channel AOHs 17 optical channels at present Spare fibre storage solution was not optimum and has been improved in the final version. 8 Layer board: 2 signal, 4 power and 2 ground

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Temperature control implemented AOH temperature control achieved by varying power to a heating resistor. Temp sensor measures AOH temperature via thermal bridge Perspex part of AOH support (not visible) insulates it from the PCB Power dissipated here and conducted to AOH via thermal bridge Combined ADC & DAC measures temperature and modulates heating power FPGA measures temperature, performs PID calculation to calculate heating power required I2C bus

LECC2003: The 96 Chann FED Tester: Greg Iles30 September APV frame pattern generation –Limited amount of RAM available on FPGAs. –The 6 virtual APVs access the same frame pattern memory (233 frames deep). The pointer memories are 1k deep and loop over. –The pattern and pointer memories can be updated “on the fly”. APV frame memory APV frame pointer memory The frame pattern memory is accessed at 120MHz. Multiplexer and variable data delay APV frame pointer memory Multiplexer and variable data delay Multiplexer 20MHz Sort 20MHz40MHz

LECC2003: The 96 Chann FED Tester: Greg Iles30 September FED Tester capabilities –96 optical channels, of which 12 are unique (3x4 internal, 1x4 external). –Each AOH channel can be delayed by up to 32 clks to a nominal granularity of 100ps. –New FED test data can be uploaded to the FED Tester without stopping system. –AOH temperature control system guarantees temperature stability regardless of lab temperature fluctuations (within limits) –Inbuilt Trigger Control System (TCS) provides L1Reset, L1A, BC0, Event Counter Reset, etc –System is flexible because FPGAs can be reprogrammed and control system allows for expansion. –Daughter card area allows for expansion (e.g. TTC) with 64 digital IO (32 if LVDS) and power +5V, +3.3V, +2.5V and 1.5V.

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Data recorded by FED FED Tester driving all 12 fibres of FED front-end unit 0 Missing data from Channel 1 is still under investigation. Digital header Analogue data including “hit”

LECC2003: The 96 Chann FED Tester: Greg Iles30 September Conclusions Current Status: –The prototype FED is already being used to debug FED firmware & software. –A further 4 FED Testers are in manufacture so that we can drive all 96 channels of a FED. FED Tester FED