3 차원 구조의 고집적 charge trap 플래시 메모리 개발 1/ 년 xx 월 xx 일 School of EE, Seoul National University 대표 학생김승현 과제 책임자박병국 교수님

연구 성과 요약 (’10.07~’15. 06) 1. 참여 기간 : ~ 현재 2. 전략산학 장학생 현황 : 정성헌, 김장현, 박의환, 김승현, 김성준 ( 총 5 명 ) 3. 대표 연구 주제 : - Gated Twin-Bit (GTB) SONOS 제안 및 구현 - Gated Multi-Bit (GMB) SONOS 제안 - Retention characteristics caused by charge loss in Charge trap memory 분석 5 년간 전략산학 연구 성과 결산 2/12

3/12 대표 논문 Review 논문 제목 : - Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory 논문 내용 : -3 차원 구조의 고집적 charge trap 플래시 메모리인 gated twin-bit SONOS memory 제안. 하나의 cut-off gate 와 각 wordline 마다 두개의 memory node 를 가지 는 특징을 지니고 있다. 집적도를 더욱 높이기 위해 ver tical 방향으로 poly silicon gate 를 집적할 수 있다. 저널 정보 : - 저널명 : IEEE TRANSACTIONS ON NANOTECHNOLOGY

4/12 Gated Twin-Bit (GTB) SONOS Introduction BL1 BL2 BL3 WL1WL2WL3 2F BL1 BL2 BL3 WL1WL2WL3 2F BL1 BL2 BL3 WL1 WL2 2F WL3 WL4 WL5 WL6 2F Conventional NAND array : 1 bit per 4F 2 Folded NAND array : 2 bit per 4F 2 Disadvantage : large feature size F  2 WL and isolation space is required. Gated Twin-Bit (GTB) NAND array : 2 bit per 4F 2

Program Operation of Gated Twin-Bit Array 5/12 Program operation … SSL CUT- OFF1 WL1 DSL BL CUT- OFF64 WL64 BL’ BL BL’ BL BL’ … SSL CUT-OFF1 WL1 DSL BL’ CUT-OFF 64 WL64 BL ON V DD ON0 V V DD 0 V boosted CUT-OFF n WL n … OFF PGM Inhibit WL1WL2WL3 CUT1CUT2CUT3 DSLSSL 0 V 3 V AA’ Vpgm Vpass

Read Operation of Gated Twin-Bit Array 6/12 Read operation CONTROL LINE READ (WL2) WL1(unselected)HIGH WL2(selected)0 V WL3(unselected)HIGH Cufoff-G1HIGH Cufoff-G2HIGH Cufoff-G3HIGH SSLHIGH L side of BL1(selected)GNDV DD R side of BL1(selected)V DD GND L side BL2(unselected)GND R side BL2(unselected)GND SubstrateGND V DD GND READ reverse reading FORWARD, REVERSE READ SCHEME : similar to NROM (NOR Flash) … SSL CUT-OFF1 WL1 DSL BL’ CUT-OFF 64 WL64 BL ON V DD 0 V CUT-OFF n WL n … ON READ V PASS 0 VV PASS … SSL CUT-OFF1 WL1 DSL BL’ CUT-OFF 64 WL64 BL ON 0 V V DD CUT-OFF n WL n … ON READ V PASS 0 VV PASS

Read Operation of Gated Twin-Bit Array 7/12 Read operation (Node L read condition : V BL = 2V, V control = 0 V) 11 state 00 state Node L Node R 01 state Node LNode R 10 state Node L Node R L node = 40 nm CUT-OFF n WL n 0 V 2 V 0 V 2 V 00PP 01PE 10EP 11EE 10 state : drain induced barrier lowering  Effect of node R decrease.

Measurement of fabricated device 8/12 Cut-off gate characteristics  Current flow is absolutely blocked when 0 V is applied to the Cut-off gate The channel is cut successfully between the left and right side of the control gate. Separate programming is possible.

Measurement of fabricated device 9/12 Control gate characteristics with drain voltage  V T difference increases as the V D increases  imply the barrier lowering # Simulation data If same amount of charge is injected with fabricated device, L node (nm)3040Fabricated device V T,F -V T,R (V)  L node of fabricated device is estimated at 4x nm. (V D =2 V)

Measurement of fabricated device 10/12 Control gate characteristics: 2 bit expresssion ERS PGM  V T of 11,10 state and 01,00 state is clearly distinguished. : Twin-bit operation is verified.

Gated Multi-Bit (GMB) SONOS Array 11/12 Gated Multi-Bit (GMB) Gated Twin-Bit (GTB) 1. Minimum silicon trench width = 2 × (ONO thickness) + polysilicon gate thickness 2. Thin silicon pillar thickness  leakage current  Limit to extreme scaling down of feature size (F) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8  2×n bit / 4F 2 (n = the number of the stacked layers)  Single crystalline channel with stacked gates Transactions on Nanotechnology, March, 2012

향후 계획 5 년간 주요 연구 성과 - Gated Twin-Bit (GTB) SONOS 제안 및 구현 - Gated Multi-Bit (GMB) SONOS 제안 - Retention characteristics caused by charge loss in Charge trap memory 분석 12/12