Chapter 8. Additional Topics in VHDL 권동혁

Contents 1.Attributes 2.Transport and Inertial Delays 3.Operator Overloading 4.Mulitvalued Logic and Signal Resolution 5.IEEE-1164 Standard Logic 6.Generics 7.Generate Statements 8.Synthesis of VHDL Code 9.Synthesis Examples 10.Files and TEXTIO

1. Attributes S ’ EVENT : “ S tick EVENT ”, S is signal name S 가 변하면 TRUE S ’ ACTIVE : returns TRUE if S has just been re- evaluated, even if S does not chang.

2. Transport and Inertial Delays Transport Delay : delays an input signal by the specified delay time. (delay introduced by wiring) Inertial Delay : default delay type. 입력에서의 short pulse 는 출력으로 propagate 안됨. Gate 와 같은 device 를 modeling. (inertial delay T : 폭이 T 보다 짧은 pulse 는 reject 됨.)

Signal_name <= reject pulse-width expression after delay- time Z1 <= transport X after 10 ns; -- transport delay Z2 <= X after 10 ns; -- inertial delay Z3 <= reject 4 ns X after 10 ns; -- delay with specified -- rejection pulse width Zm <= X after 4 ns; -- inertial delay rejects short pulses Z3 <= transport Zm after 6ns; -- total delay is 10 ns

sequential statements A <= transport B after 1 ns; A <= transport C after 2 ns; ---> 차례로 수행 A <= B after 1 ns; -- inertial delay implied A <= C after 2 ns; -- inertial delay implied ---> the change to B is removed from the queue, only the change to C occures A <= transport B after 2 ns; A <= transport C after 1 ns; ---> the previous change to B is removed from the queue, only the change to C occures.

3. Operator Overloading arithmetic operators, + and - : integer operation. not on bit-vector operation operator overloading : "+" operator implicitly call an appropriate addtion function. ex) procedure Addvec 대신에 bit_vector 계산에 operator 로 + 를 사용하고 function "+" 를 별도로 정의하여 사용함. A <= B + C + 3;  A,B,C 가 integer 이면, excute integer arithmetic operation.  A,B,C 가 type bit_vector 이면, 두가지 overloading function call A <= 3 + B + C;  compile-time error. (integer + bit_vector 를 위한 function 없음 )

4. Multivalued Logic and Signal Resolution two-valued bit logic : 0, 1 multivalued logic : 0, 1, Z, X,... resolution function : 2 개 이상의 source 로부터 출력이 관련될 때 실제 출력을 결정. a=c=d=1,b=0  f=Z, 1  resolution functions 이 자동으로 call 되어 f=1 로 결정하게 됨.

VHDL signal ---1)resolved signal : resolution function 을 가진 신호 2)unresolved signal : resolution function 이 없는 신호 R <= transport '0' after 2 ns, 'Z' after 6 ns; R <= transport '1' after 4 ns; R <= transport '1' after 8 ns, '0' after 10 ns;

5. IEEE-1164 Standard Logic specifies a 9-valued logic system 'U' - Uninitialized, 'X' - Forcing unknown, '0' - Forcing 0 '1' - Forcing 1, 'Z' - Hige Impedance, 'W' - Week unknown 'L' - Weak 0, 'H' - Weak 1, '-' - Don't care forcing signal and weak signal is tied : forcing signal dominates. useful in modeling the internal operation of certain type of ICs. IEEE-1164 standard : defines the AND, OR, NOT, XOR, other fuction for 9-valued logic

6. Generics commonly used to specify parameters for a component

7. Generate Statements When an iterative array of identical components is required, an easy way of instantiating these components. At compile time, a set of concurrent statement(s) is generated ex) generate_label: for identifier in range generate [begin] concurrent statement(s) end generate [generate_label]; generate_label: if condition generate [begin] concurrent statement(s) end generate [generate_label];

8. Synthesis of VHDL Code CAD tools : VHDL description => circuit description ( logic schematic, wirelist, gates, flip-flops, registers, counters, multiplexers, adders,....) synthesis tools : VHDL description => implement using PGA or CPLD VHDL code compiles and simulates correctly ≠ synthesize correctly. => synthesis tool 이 designer 의 의도를 이해하도록 VHDL code 변경. => efficient implementation 을 위한 추가적인 변경이 필요. ex) A <= B and C; -- A implemented using combinational logic wait for clock'event and clock = '1'; A <= B and C; -- A represents a register(or flip-flop), rising edge -- of the clock.

VHDL signal 에 값이 assign 되면 새로운 값이 배정될 때 까지 그 값이 유지 => synthesizer 가 latch 로 인식. * a 가 3 이면 ? b 의 previous value 가 유지되야함.--> latch 사용. * null 대신에 b<='0' 로 바꾸면 latch 를 제거할 수 있다. b=a 0 ' = D a=3 이면 b=previous value, G=0, --> G=(a 1 a 0 )'

if 문 사용시 주의 if A = '1' then Nextstate <= '3'; end if; -- designer : A ≠ '1' 이면 Next state 는 이전상태 값 유지. -- sinthesizer : A ≠ '1' 이면 Next state 는 unkwon('X') --ambiguous. if A = '1' then Nextstate <= '3'; else Nextstate <= '2'; -- unambiguous end if; speed 최적화 => 부품의 수가 증가 (max. propagation delay 의 path 길이를 짧게 ). ex)3-level gate network ->2-level network : gate 수 증가. 지연 감소 area 최적화 => 부품수 감소.( 필요한 chip area 감소 )

Synopsis Design Compiler : case 문 ==> MUX, gates. b 1 = a 1 'a 0, b 0 =a 1 ' + a 0

standard VHDL : not provide for arithmetic opeartion on bit- vectors.  function 이나 procedure 사용 (Add4, Addvec) IEEE : bit_vectors, std_logic vectors 에서 arithmetic operation 을 할 수 있는 function 을 포함하는 standard synthesis package 개 발. (numeric_bit package, numeric_std package) numeric_bit, numeric_std package 가 정의하는 overloaded opeartors: 1)Unary: abs, - 2)Arithmetic: +, -, *, /, rem, mod 3)Relational: >, =, <=, =, /= 4)Logical: not, and, or, nand, nor, xor, xnor 5)Shifting: shift_left, shift_right, rotate_left, rotate_right, sll, srl, rol, ror

9. Synthesis Examples 2 개의 CAD system 으로 VHDL code synthesizing 비 교 ( Synopsis Design Compiler with XACT libraries, Altera Max- Plus II VHDL compiler) fig2-13 을 수정하여 fig8-18 을 적용 - Synopsis Design Compiler using generic libraries : 3 flip-flops, 13 gates. (Chapter 1 의 designed circuit : 7 gates) - Synopsis Design Compiler using IEEE standard logic : 12 gates. - Xilinx libraries and XC4000 PGA : 2 CLB.(8 gates, 1 XNOR or 11 gates : fig8-19) - Altera Max-Plus II VHDL compiler with MAX 7000 CPLD : 9 logic cells. => when s6 문과 when others 문을 변경하여 4 logic cells 로 줄임. ( a small change in the code => a large change in the amount of resources used)

Dice game(fig 5-11, fig 5-13) 예제 - S ynopsis Design Compiler : 27.5 CLBs. => behavioral model 을 data flow model 로 변 경하여 25 CLB. - Altera Max-Plus II VHDL compiler with MAX 7000 series : 39 logic cells 와 34 shareable expanders. =>data flow model 로 변경 후 38logic cells 와 25 sharable expander. => VHDL code 변경 : 31 logic cells and 13 shareable expanders (fit into a 7032 chip)

10. Files and TEXTIO standard TEXTIO package : can be used to read or write lines of text from or to a file. file 사용을 위한 선언 file file-name : file_type [open mode] is "file_pathname"; file test_data : text open read_mode is "c:\f2 test.dat"; mode : read_mode, write_mode, append_mode a file can contain only one type of object - integers, bit_vectors, text strings. type bv_file is file of bit_vector; endfile(file_name) --each file type has implicit endfile function

type text is file of string; --TEXTIO package 에서 text type 을 정의 type line is access string; -- line is the pointer to the buffer. variable buff : line; readline (buff, test_data); -- test_data 에서 text 1 line 을 읽어 buff 가 point 하는 buffer 에 놓는다. buff 는 buffersp 의 다음 text 를 point 한 다. read (point, value); read (point, value, good); variable buffw: line; variable int1: integer; variable bv8: bit_vector(7 downto 0); write(buffw, int1, right, 6); -- int1 을 string 으로 바꿔 buffw 가 point -- 하는 buffer 에 right-justify 해서 6 character wide 로 write. -- buffw 는 adjust 되어 다음을 point 함. write(buffw, bv8, right, 10); writeline(buffw, output_file); -- output_file 로 buffer 내용을 write.

ex) file 내용이 다음과 같다. fill_memory procedure is called. 12AC 7 (7 hex bytes follow) AE 03 B6 91 C7 00 0C (LDX imm, LDA dir, STA ext) 005B 2 ( 2 hex bytes follow) 01 FC