MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France MIMO Hardware Simulator Design for Outdoor Time-Varying Heterogeneous Channels B. Habib, G. Zaharia, G. El Zein IETR / INSA Rennes, France ISSCS 2013 July 2013 B. Habib, G. Zaharia, G. El Zein IETR / INSA Rennes, France ISSCS 2013 July

Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions et prospects Outline Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 2

Why do we need a hardware simulator? TXTX RXRX » Provides the necessary speed. » Repetition of the tests. » Performance evaluation. » Compare the performance of various systems. » Reproduce many types of environments: Hardware Simulator (Designed on FPGA ) x1x1 x2x2 h 11 h 22 h 21 h 12 y1y1 y2y2 Why do we need a hardware simulator? Hardware simulator characteristics MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 3 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects

Hardware simulator characteristics Frequency domain architecture Time domain architecture Precision Latency Slices occupation Recorded data: - Ray tracing method - Channel sounder realized at the IETR: -… Standard models: - TGn channel models - 3GPP-LTE channel models - … MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 4 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Why do we need a hardware simulator? Hardware simulator characteristics

TGn channel models ¹ » 6 models (indoor) » IEEE ac standard » fs = 165 MHz (B = 80 MHz) ¹ V. Erceg, L. Schumacher, P. Kyritsi, et al., “TGn Channel Models”, IEEE Tech. Rep /940r4, May 10, Model B for a typical office environment Model E for a typical indoor large open space environment MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 5 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Channel models Proposed scenario

3GPP-LTE channel models ² ¹ V. Erceg, L. Schumacher, P. Kyritsi, et al., “TGn Channel Models”, IEEE Tech. Rep /940r4, May 10, ²Agilent Technologies, “Advanced design system – LTE channel model - R GPP TR v0.3.0”, MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 6 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Channel models Proposed scenario » 3 models (outdoor) » LTE standard » fs = 50 MHz (B = 20 MHz) Extended Pedestrian A model (EPA) Extended Vehicular A model (EVA) Extended Typical Urban model (ETU) Time-varying channel¹: » Kronecker model

Algorithm to switch between environments: (between impulse reponses) » Delays and relative powers switch: » Refresh frequencies switch: Proposed scenario MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 7 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Channel models Proposed scenario

Time domain architecture MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 8 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Time domain architecture Implementation on FPGA 2 x 2 MIMO architecture: Sliding window truncation:

Implementation on FPGA MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 9 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Time domain architecture Implementation on FPGA

Theoretical input and output signals MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 10 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Theoretical input and output signals SNR Gaussian input signal: Theoretical output signals:

FPGA output signals and SNR MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 11 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Theoretical input and output signals SNR Snapshots of the FPGA output signal y 1 for E 1,E 2 and E 3 : SNR:

Conclusions MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 12 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Conclusions Prospects - Digital block of hardware simulator: » 2 x 2 MIMO time domain architecture » Sliding window truncation - Simulation of a scenario: » With 3GPP-LTE channel models » Algorithms to switch between environments -The time domain architecture has: » Low occupation on FPGA » Low latency » High output signals precision -The proposed algorithms affect the channel models used by the hardware simulator; they allow to switch between the environments in a continuous manner

Prospects MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France 13 Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects Conclusions Prospects » Implementation on more performing FPGA (Virtex VII)  High MIMO order » Measurements campaigns for specific environments » Simulation for different scenarios for heterogeneous environments and networks

Thank you Testing the architecture with real impulse response carried out with the MIMO channel sounder realized by IETR. MIMO Hardware Simulator Design – ISSCS 2013IETR, UMR CNRS 6164 / INSA Rennes, France Hardware simulator principle Channel models and simulated scenario Digital block architecture Output signals accuracies Conclusions and prospects