1 Clarinet: A noise analysis tool for deep submicron design Rafi Levy Gabi Bracha, David Blaauw, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov Motorola, Inc., Austin,TX. Motorola Semiconductor Israel, Ltd.

2 2 Noise Problems u Noise analysis is important for high performance design: –Non-uniform scaling of interconnects –Noise sensitive circuit structures –Fast edge rates u Noise types: –Functional noise: victim is stable –Delay noise: victim is switching This presentation will focus on functional noise only.

3 3 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions u Results u Conclusions

4 4 Noise Analysis Challenges u Large run time –Analyze large number of nets. »For each net load and analyze large number of interconnect data. –Non-linear problem due to the non linearity of the driving gates. u Large number of false violations –Need to reduce pessimism by accounting for timing and logic correlation. We discuss a new analysis tool called ClariNet which addresses these challenges.

5 5 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions u Results u Conclusions

6 6 Clarinet Approach and Flow VnVn u Previous work: propagation approach [SHEP97] u Our approach: analyze each net independently: assume fixed amount of noise V n generated by the previous stage. 1. Apply noise filters to quickly eliminate victim nets with insignificant noise. 2. Generate linear models for aggressor and victim drivers. 3. Simulate each aggressor on the resulting linear circuit with PRIMA. 4. Determine worst set of aggressors - accounting for logic and timing constraints. 5. Combine noise from different aggressors + V n at the victim net sink using superposition, then propagate the noise through the receiver gate. Vdd-V n VnVn

7 7 Clarinet Approach and Flow v v u Previous work: propagation approach [SHEP97] u Our approach: analyze each net independently: assume fixed amount of noise V n generated by the previous stage. 1. Apply noise filters to quickly eliminate victim nets with insignificant noise. 2. Generate linear models for aggressor and victim drivers. 3. Simulate each aggressor on the resulting linear circuit with PRIMA. 4. Determine worst set of aggressors - accounting for logic and timing constraints. 5. Combine noise from different aggressors + V n at the victim net sink using superposition, then propagate the noise through the receiver gate.

8 8 Clarinet Approach and Flow v u Previous work: propagation approach [SHEP97] u Our approach: analyze each net independently: assume fixed amount of noise V n generated by the previous stage. 1. Apply noise filters to quickly eliminate victim nets with insignificant noise. 2. Generate linear models for aggressor and victim drivers. 3. Simulate each aggressor on the resulting linear circuit with PRIMA. 4. Determine worst set of aggressors - accounting for logic and timing constraints. 5. Combine noise from different aggressors + V n at the victim net sink using superposition, then propagate the noise through the receiver gate.

9 9 Clarinet Approach and Flow v u Previous work: propagation approach [SHEP97] u Our approach: analyze each net independently: assume fixed amount of noise V n generated by the previous stage. 1. Apply noise filters to quickly eliminate victim nets with insignificant noise. 2. Generate linear models for aggressor and victim drivers. 3. Simulate each aggressor on the resulting linear circuit with PRIMA. 4. Determine worst set of aggressors - accounting for logic and timing constraints. 5. Combine noise from different aggressors + V n at the victim net sink using superposition, then propagate the noise through the receiver gate.

10 Clarinet Approach and Flow v v u Previous work: propagation approach [SHEP97] u Our approach: analyze each net independently: assume fixed amount of noise V n generated by the previous stage. 1. Apply noise filters to quickly eliminate victim nets with insignificant noise. 2. Generate linear models for aggressor and victim drivers. 3. Simulate each aggressor on the resulting linear circuit with PRIMA. 4. Determine worst set of aggressors - accounting for logic and timing constraints. 5. Combine noise from different aggressors + V n at the victim net sink using superposition, then propagate the noise through the receiver gate.

11 Clarinet Approach and Flow VnVn Vdd-V n VnVn u Previous work: propagation approach [SHEP97] u Our approach: analyze each net independently: assume fixed amount of noise V n generated by the previous stage. 1. Apply noise filters to quickly eliminate victim nets with insignificant noise. 2. Generate linear models for aggressor and victim drivers. 3. Simulate each aggressor on the resulting linear circuit with PRIMA. 4. Determine worst set of aggressors - accounting for logic and timing constraints. 5. Combine noise from different aggressors + V n at the victim net sink using superposition, then propagate the noise through the receiver gate.

12 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Accurate Victim Driver Model –Handling of Multiple Drivers –Noise Filters –Aggressor Pruning –Timing and Logic Correlation u Results u Conclusions

13 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Accurate Victim Driver Model »Algorithm to detect worst case driver input vectors. »Algorithm to determine min/max driver voltage due to Vt drop. –Handling of Multiple Drivers –Noise Filters –Aggressor Pruning –Timing and Logic Correlation u Results u Conclusions

14 Victim driver model u Victim driver has a stable state –modeled by a simple resistance (holding resistance). u Worst noise occurs with maximum holding resistance –must find input vector of maximum resistance and compute its equivalent resistance. –can be solved by enumerating all input vectors or by doing path traversals. R hold a b b a c a out=high out ab = 01 ab = 00 R hold1 R hold2 right pull-up path ON both pull-up paths ON

15 Determine worst-case Input Vectors H x = a * b + a + c = a + c L x = a * c * (a + b) = a * c G x = H x * L x = a + c a 1 0 c BDD G x paths to leaf 1: {a=0}: p1,p3 ON After expansion: {a=0, b=1, c=1}: p2,p4 OFF {a=1, c=0}: p4 ON, p1,p3 OFF After expansion: {a=1, b=1, c=0}: p2 OFF Construct BDD Gx = H x * L x for x=1. For each satisfiable path to leaf node 1: Create a partial input vector and assign values to known gate nodes. Expand unknown gate nodes in partial vector if they have safe assignments. Safe assignment turns transistors OFF without turning ON remaining transistors. Enumerate remaining unknown gate nodes. x = 1 a b a c ab p1 p2 a p3 c p4

16 Holding Resistance Calculation For each gate’s input vector, determine holding resistance: 1. represent each ON transistor by its equivalent resistor (pre-calibrate holding R as a function of W) 2. disconnect all other transistors. 3. perform iterative series/parallel reduction and star-delta transformations. u We account for noise in holding R pre-calibration by setting V ds = V allowable where V allowable is the expected worst-case allowable noise

17 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Accurate Victim Driver Model »Algorithm to detect worst case driver input vectors. »Algorithm to determine min/max driver voltage due to Vt drop. –Handling of Multiple Drivers –Fast Noise Filters –Aggressor Pruning –Timing and Logic Correlation u Results u Conclusions

18 Victim voltage calculation u Special driver circuits do not drive the net to full Vdd or Gnd voltage due to Vt drop. –net has already DC noise equivalent to the voltage drop. –holding R is very large. u Detect min/max voltage of a victim driver –use max voltage as the initial victim voltage for low-overshoot and high-overshoot –use min voltage as the initial victim voltage for low-undershoot and high undershoot. b gnd a max = Vdd out = high vdd ad = 00 n1 OFF, P1 ON ad = 11 n1 ON, p1 OFF min = Vdd - Vt d n1 p1

19 Victim Voltage Calculation Construct G x = H x *L x for x = 1 2. Construct F x = p x *L x where p x is the pull-up function of the driver gate with all NMOS transistors disconnected. The function F x represents the input vectors that result in a high output state without any Vt drop. The function G x * F x determines if voltage drop is possible. u Determine voltage drop according the following table.

20 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Victim Driver Model –Multiple Drivers –Noise Filters –Aggressors Pruning –Timing and Logic Correlation u Results u Conclusions

21 Multiple Aggressor Drivers u When more than 1 driver is connected to an aggressor: –One or more driver can be simultaneously active –Assuming all to be active is overly conservative u Our approach: –Determine whether each driver is tristate and non-tristate. –Non-tristate drivers: all are active. –Tristate drivers: only the strongest driver is active. –Use superposition for all active drivers. a d e b c worst

22 Multiple Victim Drivers u When more than 1 driver is connected to a victim: –One or more can be simultaneously holding victim stable. –Consider only the weakest driver is too pessimistic. u Our approach: –Non-tristate drivers: all are active. –Tristate drivers: all are inactive. –If all drivers are tristate: simulate. b c c b a d

23 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Victim Driver Model –Multiple Drivers –Noise Filters –Aggressors Pruning –Timing and Logic Correlation u Results u Conclusions

24 Noise Filters u Why we need efficient noise estimation techniques: –Cost of loading and simulating interconnect and cross-talking elements is extremely high. –Cost of generating accurate driver models is expensive. –Large number of nets in circuit with a small fraction suffer from noise. u Previous work: Analytical filters proposed by : –Requires an expensive loading [DEV97], [KUHL99] –Too conservative for fast aggressors [DEV97] u We propose a simple structural filtering –Apply three successive filters until either the victim net passes or fails (compared to V threshold ) all the filters and is simulated in full detail. –Each successive filter is less conservative but requires longer run-time.

25 Structural Filters - 1 u Use default aggressor and victim driver models u Applied on entire net - use lumped values u Can be solved analytically R thev = R default / N v R hold R net C couple C ground N = number of aggressors C couple = sum of coupling caps for victim C ground = sum of grounded caps for victim R net = sum of resistances of victim R hold = default victim driver holding R R default = default aggressor driver thevenin R t default = default aggressor slope t default

26 Structural Filters - 2 u Use accurate victim driver model, default aggressor model u Victim topology is loaded in detail u Applied on each victim source/sink pair R side R thev = R default / N v R hold R path C couple C ground_path C ground_side N = number of aggressors C couple = sum of coupling caps for victim R default = default aggressor driver thevenin R t default = default aggressor slope C ground_path = sum of grounded caps for source-sink path R path = resistance of source-sink path C ground_side / R side = side branch caps / Rs R hold = victim driver holding R t default

27 Structural Filters - 3 u Use accurate aggressor and victim driver models u Both the victim and aggressor topologies are loaded R side R thev = || R thevenin v R hold R path C couple C ground_path C ground_side R side_agr C ground_agr C couple = sum of coupling caps for victim C ground_path = sum of grounded caps for souce-sink path R path = resistance of source-sink path C ground_side / R side = side branch caps / Rs R hold = victim driver holding R R side_agr = aggressor side branch Rs C ground_agr = aggressor grounded caps R thevenin = aggressor driver thevenin R t thevenin = fastest aggressor driver slope t thevenin

28 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Victim Driver Model –Multiple Drivers –Noise Filters –Aggressors Pruning –Timing and Logic Correlation u Results u Conclusions

29 Aggressor Pruning u Number of aggressors in a noise cluster can be large. –Can make simulation infeasible. –Large number aggressors contribute a very small amount of noise. u ClariNet pruning options: –Select N worst highly coupled aggressors. –Discard all aggressors that have a ratio between coupling cap to victim grounded cap less than user specified threshold. –Use approximate noise estimation (Filter 1) of small aggressors, and discard aggressors until total noise exceeds user specified noise threshold. This guaranteed that all non-contributed aggressors are removed and the noise error is below a threshold. u We ground discarded coupling caps.

30 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions –Victim Driver Model –Multiple Drivers –Noise Filters –Aggressors Pruning –Timing and Logic Correlation »Consider static and sensitivity windows for victim nets. »New algorithm to enumerate the number of aggressor subsets u Results u Conclusions

31 Timing Windows u Timing correlation constraints (high-undershoot) –aggressors switching (falling) –Victim is stable (high) –Noise can be propagated into a latch u Traditionally activity windows for aggressors are used. –Activity window: window in which the net can switch (fall / rise) u We propose to consider static and sensitivity windows for victim. –Static window (high / low) »Used for clocks. –Sensitivity window for victim sink (low-overshoot, high-undershoot) »Sensitivity window: window in which the noise from that sink can propagate into a latch.

32 Logic Correlation u Logic correlation constraints (high-undershoot) –switching of aggressors in the same direction (falling) –Victim in a stable state (high) u User specified logic correlation in ClariNet: –inversion, same, imply –one-hot, one-cold u Logic correlation under zero delay is not conservative –using logic functions cannot detect glitch –Specify pair wise logic relations across single gates.

33 Logic Correlation & Timing Windows Algorithm u Examine High-undershoot noise u Construct BDD by ANDing the logic constraints. u Reduce BDD by asserting the victim logic state. (High) u For each pair of satisfiable paths p1 != p2: –p1 and p2 correspond to logic constraints before and after the aggressors switch. –Identify a subset S of MUST_SWITCH aggressors - aggressors with opposite polarity in p1 and p2 that match the intended transition. (Falling). –Add MAY_SWITCH aggressors to S - aggressors that do not appear in p1 and p2. –Intersect timing windows of aggressors in S to find an intersection with max noise. BDD = (a -> b) * (bc + bc) = bc + abc c b c b c a 0 a b c victim p1 = bcp2 = bc

34 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions u Results u Conclusions

35 Results - Circuit Characteristic and Analysis 1

36 Outline u Noise Challenges u Clarinet Approach and Flow u Clarinet Contributions u Results u Conclusions

37 Conclusions u We have presented a new functional noise analysis tool. u We have presented new algorithm for critical issues in noise analysis: –Efficient and accurate modeling of the victim driver gate –Noise filters for speeding up run time –Timing and Logic Correlation for reducing number of false noise violations u We demonstrated the tool on a number of industrial designs. u The use of noise filters + aggressor pruning allow us to analyze 400 thousands nets under 6 hours