SYSTEM-LEVEL TEST TECHNIQUES INTRODUCTION In the 1970s, the in-circuit testing (ICT) method appeared. In the 1970s, the in-circuit testing (ICT) method appeared. Mechanical testing becomes difficult with board trace widths ard separations Mechanical testing becomes difficult with board trace widths ard separations below 0.1 mm or 100 Jam. below 0.1 mm or 100 Jam. In 1985 a group of European manufacturer formedthe Joint European Test Action Group (JETAG) to study board testing. In 1985 a group of European manufacturer formedthe Joint European Test Action Group (JETAG) to study board testing. In 1986 JETAG becomes Joint Test Action Group (JTAG) with the addition of North American Companies. In 1986 JETAG becomes Joint Test Action Group (JTAG) with the addition of North American Companies. The main virtue of the standard can be used by board designers, IC designers, and systems dejgners. The main virtue of the standard can be used by board designers, IC designers, and systems dejgners. without the need for members of each design community to fully understand the testing problems of the other communities. without the need for members of each design community to fully understand the testing problems of the other communities.

BOUNDARY SCAN Boundary scan is actually a collection of design rules, applied at the IC level for testing hoards using a four-wire interface (five wires with an optional master reset signal). Boundary scan is actually a collection of design rules, applied at the IC level for testing hoards using a four-wire interface (five wires with an optional master reset signal). Boundary scan provides the following major modes of operation: Boundary scan provides the following major modes of operation: These resources enable asynchronous communication with the outside world to serially read in test data and instructions or serially read out test results. These resources enable asynchronous communication with the outside world to serially read in test data and instructions or serially read out test results. The activities are invisible to the normal IC behaviour. The activities are invisible to the normal IC behaviour. The pin-permission modes of the standard take control of the IC input/output pins, thus disconnecting the system logic from the outside world. The pin-permission modes of the standard take control of the IC input/output pins, thus disconnecting the system logic from the outside world. These modes allow testing of the system interconnect separately from component testing. These modes allow testing of the system interconnect separately from component testing. And also allow testing of components separately from system interconnect testing. And also allow testing of components separately from system interconnect testing. The testing actvities totally disrupt the normal IC behaviour. The testing actvities totally disrupt the normal IC behaviour.

SYSTEM CONFIGURATION WITHBOUNDARY SCAN It is integrated circuit that is complaint with the boundary- scan standard. It is integrated circuit that is complaint with the boundary- scan standard. Note that on each pin of the chip, there is internal hardware that provides a register dt that pin position. Note that on each pin of the chip, there is internal hardware that provides a register dt that pin position. The serial connection of these registers around the periphery of the chip at the pins is known as the boundary register The serial connection of these registers around the periphery of the chip at the pins is known as the boundary register The input to a boundary-scan shift register is the test-data input (TDI). The input to a boundary-scan shift register is the test-data input (TDI). The output of a boundary-scan shift register is the test-data output (TDO). The output of a boundary-scan shift register is the test-data output (TDO).. The boundary-scan shift register in each IC is one of several test- data registers (TDR) that may included in each IC.. The boundary-scan shift register in each IC is one of several test- data registers (TDR) that may included in each IC. All the TDRs in an IC are connected dirctIy between the TDI and TDO ports. All the TDRs in an IC are connected dirctIy between the TDI and TDO ports. The Device ID register provides the device identification. The Device ID register provides the device identification. The bypass register bypasses the boundary register for this component. This is useful when all boundary registers of all components on the PCB are chained together into one long shift registers, and it is desired to reduce the length of the register by ignoring hardware on components that are not involved in the current test. The bypass register bypasses the boundary register for this component. This is useful when all boundary registers of all components on the PCB are chained together into one long shift registers, and it is desired to reduce the length of the register by ignoring hardware on components that are not involved in the current test.

SCHAMATIC OF SYSTEM TEST LOGIC

BST CELLS That may be used to implement any of the TDRs. That may be used to implement any of the TDRs. The most common DR cell is a boundary-scan cell. The most common DR cell is a boundary-scan cell. A BSC contains two sequential elements. A BSC contains two sequential elements. (i) The capture flip-flop or capture register formed by series Connection of BCs. (i) The capture flip-flop or capture register formed by series Connection of BCs. (ii) The update flip-flop, or update FF Latch is an edge-triggered D flip-flop. (ii) The update flip-flop, or update FF Latch is an edge-triggered D flip-flop.

THE INPUTS TO A BSTARE: Scan in (serial in or SI) Scan in (serial in or SI) data in (parallel in or P1) data in (parallel in or P1) Control signal, mode (also called test/normal). Control signal, mode (also called test/normal). THE BST OUTPUTS ARE: THE BST OUTPUTS ARE: Scan out (serial out or SO) Scan out (serial out or SO) data out (parallel out or P0) data out (parallel out or P0) The sequential logic in a BSC controlled by the gated clocks: clockDR and updat)R. The sequential logic in a BSC controlled by the gated clocks: clockDR and updat)R.

BYPASS-REGISTER CELL (BR) The BR inputs and outputs, The BR inputs and outputs, SCAN SCAN in (serial in, SI) and scan out (Serial out, SO), have the same names as the DR cell ports, in (serial in, SI) and scan out (Serial out, SO), have the same names as the DR cell ports, but DR cells and BR cells are not directly connected. but DR cells and BR cells are not directly connected. INSTRUCTION - REGISTER CELL INSTRUCTION - REGISTER CELL THE JR CELL INPUTS ARE: THE JR CELL INPUTS ARE: scan in scan in data_in data_in Clock Clock Shift Shift update signals update signals reset signals reset signals

INSTRUCTION-REGISTER CELL (IR) INSTRUCTION-REGISTER CELL (IR) The two LSBs of data_in must permanently be set to ‘01’ this helps in checking the integrity of the scan chain during testing. The two LSBs of data_in must permanently be set to ‘01’ this helps in checking the integrity of the scan chain during testing. The update sequential element in each JR cell may be set or reset depending on reset_value. The update sequential element in each JR cell may be set or reset depending on reset_value. The JR cell outputs are: The JR cell outputs are: data_out (the instruction bit passed to the instruction decoder). scan_out (the data passed to the next JR cell in the IR) data_out (the instruction bit passed to the instruction decoder). scan_out (the data passed to the next JR cell in the IR) The instruction register has to be at least two bits long which are decoded with the following instruction. The instruction register has to be at least two bits long which are decoded with the following instruction. BYPASS This instruction is represented by an JR having all the bit positions to be zero. It is used to bypass any serial- data registers in a chip with a 1-bit register. This allows specific chips to be tested in a serial-scan chain without having to shift throught the accumulated SR stages in all the chips. BYPASS This instruction is represented by an JR having all the bit positions to be zero. It is used to bypass any serial- data registers in a chip with a 1-bit register. This allows specific chips to be tested in a serial-scan chain without having to shift throught the accumulated SR stages in all the chips.

EXTEST, external test — This instruction is represented by JR having all the bit positions to be one. Drives a known value onto each output pin to test connections between JCs. EXTEST, external test — This instruction is represented by JR having all the bit positions to be one. Drives a known value onto each output pin to test connections between JCs. SAMPLE/PRELOAD — Performs two functions: first sampling the present input value from input pad during capture; and then preloading the BSC update register output during update. SAMPLE/PRELOAD — Performs two functions: first sampling the present input value from input pad during capture; and then preloading the BSC update register output during update. IDCODE —. An optical instruction that allows the device-identification to be shifted out. IDCODE —. An optical instruction that allows the device-identification to be shifted out. INTEST.— This instruction allows for single-step testing of internal circuitry via the boundary- scan registers. INTEST.— This instruction allows for single-step testing of internal circuitry via the boundary- scan registers. RUNBIST — This instruction is used to run internal self-testing procedures within a RUNBIST — This instruction is used to run internal self-testing procedures within a The data bit may be directed to internal circuitry in the INTEST Or RIJNBIST modes (Mode=1). When mode=0, the cell is in EXTEST or SAMPLEIPRELOAD mode. The data bit may be directed to internal circuitry in the INTEST Or RIJNBIST modes (Mode=1). When mode=0, the cell is in EXTEST or SAMPLEIPRELOAD mode.

TAP CONTROLLER The following figure is TAP controller finite-state machine. The following figure is TAP controller finite-state machine. The Suffix ‘—DR’ operate on the data registers and those with suffix ‘—IR’ apply to the instruction register. The Suffix ‘—DR’ operate on the data registers and those with suffix ‘—IR’ apply to the instruction register. All transitions between states are determined by the TMS (test mode select) signal and occur at the rising edge of TCK. All transitions between states are determined by the TMS (test mode select) signal and occur at the rising edge of TCK.

BOUNDARY SCAN DESCRIPTION LANGUAGE The Boundary scan Description Language (BSDL) was added to the JTAG Boundary scan standard to provide a standard means of communicating information about the boundary scan hardware on a chip to users of the chip and to CAD tools through the VHDL hardware description language. The Boundary scan Description Language (BSDL) was added to the JTAG Boundary scan standard to provide a standard means of communicating information about the boundary scan hardware on a chip to users of the chip and to CAD tools through the VHDL hardware description language. BSDL can b used by automatic test-pattern generator to generate chip test pattern, and by high-level and logic synthesis tools to synthesize test logic. BSDL can b used by automatic test-pattern generator to generate chip test pattern, and by high-level and logic synthesis tools to synthesize test logic.

An active-low reset signal. TRST resets the state machine to the initial state. reset: Resets the JR to IDCODE reset: Resets the JR to IDCODE Select -IR: Connects a register, the IR or a TDR, to TDO Select -IR: Connects a register, the IR or a TDR, to TDO Shift4R: Selects the serial input to the capture flip-flop in the JR cells. update-IR: update the sequential element on the positive edge of TCK. Shift4R: Selects the serial input to the capture flip-flop in the JR cells. update-IR: update the sequential element on the positive edge of TCK. EXIT-IR: unknown or dirty signal. EXIT-IR: unknown or dirty signal. ShiftDR, Update-DR: Same functions as corresponding JR signals applied to the TDR ShiftDR, Update-DR: Same functions as corresponding JR signals applied to the TDR

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