I N V E N T I V EI N V E N T I V E Can innovations in Test serve as a beacon of light in a dark economy? Sanjiv Taneja VP and GM, Encounter Test

Outline Why it matters to our industry? Where it comes from? Innovation engine: what enables/sustains it? Innovations in Test –Key enabling factors and examples Global Talent Ecosystem collaboration Organization/Innovation Processes Holistic, integrated perspective Future innovation opportunities –Need for innovative solutions Summary –Innovations positively impact profitability and productivity

Industry design costs Source: IBS SoC design costs rising dramatically Costs of delay unacceptable 3 © 2009 Cadence Design Systems, Inc. All rights reserved.

Growing cost of power, packaging, and test 4 © 2009 Cadence Design Systems, Inc. All rights reserved. “The cost of test can be as much as 40 to 50% of the materials, labor and overhead (MLO) costs for a given device.” Qualcomm and Pintail Technologies 4-10X incremental costs of packaging for increasing levels of power! Source: Japanese Semiconductor Vendor

Growing complexity driving test costs Source IBS nm 90nm65nm45nm32nm22nm Feature dimension Percentage of design cost (%) Growing cost of manufacturing test as percentage of design … required to control cost and sustain growth ! …

Where does innovation come from? Role of large corporations and universities becomes even more critical Universities Established Companies/ Research labs Start-ups VC activity down from $12B in 2Q08 to $5.8B in 1Q09!

Innovation Engine Key enabling factors Ecosystem Collaboration Process & Culture Global Talent Holistic, integrated perspective

Global Talent Open Innovation Global Collaboratories Leverage talent across the globe

Innovation Engine Key enabling factors Ecosystem Collaboration Process & Culture Global Talent Holistic, integrated perspective

Process and culture Attract and retain best minds/talent Manage with rigor and discipline Demonstrate tolerance for risk and failure Reward innovation Technology Research with tight linkage to Products/Solutions

Innovation Engine Key enabling factors Ecosystem Collaboration Process & Culture Global Talent Holistic, integrated perspective

Ecosystem collaboration Power Forward Initiative leads to innovation solutions Foundry Leading Customers IP Vendor EDA

Innovative Solution for Low Power Test Test the Low Power Design, Reduce Power During Test Power Aware DFT and Modeling PD1 PD2 PTAM Reduce Power during test Test Pattern Power Validation Top PD1 Mem PD4 PD2 PMU Core PD3 SR Flows and Methodologies

Power-Aware ATPG Reduces Test-mode Power Example power reduction during scan and capture! Switching results based on large design (>70Million gates) Baseline represents traditional ATPG results without Low Power ATPG Max Scan switching was reduced by 73% –36.41% to 9.62% Max Capture Switching was reduced by 35% –33.43% to 21.57% Scan Switching Power Capture Switching Power 73% Reduction! 35% Reduction!

Customer Collaboration “Hitachi has collaborated with Cadence to deliver an innovative next-generation solution that is driven by our goals of meeting the complexity of advanced, nanometer designs, while achieving significant reduction in test cost and higher test quality. The collaboration has delivered an unparalleled 1,100x compression rate, which not only meets our own challenging manufacturing demands, but also the quality demands of customers in markets where reliability is mission-critical.” Dr. Nobuo Tamba, General Manager of Design & Development Operation, Micro Device Division, Hitachi, Ltd. 1100x test compression -- four years of industry roadmap!

University Collaboration Pattern fault model for gate-exhaustive test “Stanford CRC test experiments show that gate exhaustive test sets are higher quality and more efficient … than N-detect test sets in terms of the ability to detect defective chips and test length” Edward J. McCluskey, CRC Departments of Electrical Engineering and Computer Science, Stanford University, ITC © 2005 IEEE Gate exhaustive test set applies all possible input combinations to each gate and observes the gate response at an observation point “Z” A B C H1 H2 H3 G1 G2 J1 J2 G H J Z Test SetTest LengthSSF Cov. (%)GEC (%)Test Escapes 2-detect detect1, detect3, detect5, Gate exhaustive 1, Stanford Comparison of GEC vs. N-Detect ~4X Lower Pattern Requirement with Higher Coverage!

Innovation Engine Key enabling factors Ecosystem Collaboration Process & Culture Global Talent Holistic, integrated perspective

Formal Verification Physical Implementation/ Physical Verification ATPG (Encounter True Time) Concurrent Synthesis Logic + DFT (RC) Front End Back End Yield Diagnostics (Encounter Diagnostics) Silicon Verification RTL Foundry Logical Verification Physically-aware Timing-aware Power-Aware Silicon Test-Aware! Holistic, end-to-end perspective Predictable solution enabled by integration © 2009, Cadence Design Systems, Inc. All rights reserved worldwide. 18

Integrated solution example Minimizing scan power while meeting timing, area, functional power Target regs. feeding high- power gates and large logic cones Avoid critical nets Helps reduce scan power in shift-mode Scan Chain ~SE Concurrent optimization enabled by integration

3D Test Challenges Access at wafer (DFT architectures) Wafer Test Access (applied to single die/package) –Embedded Scan –JTAG (1149.1/6) –PTAM (Power Test Access Management) –OPCG (On Product Clock Generator) –MBIST –LBIST –Compression –Proc Monitors Embedded test access structures at logic synthesis –RTL and Gate level insertion –Analysis and optimization must be achieved during logic optimization Core Logic IO Pad/Ring

Future innovation opportunities Analog/High Speed IO Test Testing of 3-D stacking and 3-D packaging Parallel Algorithms to leverage multi-core compute platforms

Cost Quality Power Predictability Profit Ease-of-Use Productivity Product Integration Summary Test Innovations enhance profitability and productivity Industry must continue to deliver innovative products