Exploring SOPC Performance Across FPGA Architectures Franjo Plavec June 9, 2006

Motivation ● SOPC systems based on soft-core processors are becoming increasingly popular ● Altera and Xilinx dominate the FPGA market ● There is little or no independent information on performance of different FPGA architectures ● This work has two goals – Evaluate performance of different FPGA architectures for SOPC implementations – Evaluate the effect of various techniques on performance of these architectures

Methodology (I) Develop a complete SOPC system –Processor, peripherals, off-chip memory controller, interconnect –Based on our implementation of Nios architecture –Build several variants of the system Compile the system for different FPGA architectures High- Performance Low-cost AlteraStratix IICyclone II XilinxVirtex-4Spartan-3

Methodology (II) ● Use native synthesis tools – Quartus II Integrated Synthesis (QIS) and Xilinx Synthesis Technology (XST). ● Use exploration tools provided by Altera and Xilinx to obtain best performance – DSE and Xplorer ● Focus on performance – Report area for best performance

Results (Performance)

Results (Area)

Conclusions ● Average results – Virtex-4 is 7% slower than Stratix II – Spartan-3 is 34% slower than Cyclone II – Stratix II uses 13% fewer ”equivalent 4-LUTs” than the number of 4-LUTs used by Virtex-4 – Cyclone II uses 5% more 4-LUTs than Spartan-3 ● Physical synthesis is beneficial for Cyclone II, but provides very little performance improvement for Stratix II