IMPLEMENTATION OF FPGA BASED CONTROLLER FOR BLDC MOTOR K.ALFONI JOSE, 10B01D4302, II M. Tech(PE). Under the Esteemed Guidance of Mrs. S.M.PADMAJA, Asso. Prof Department of Electrical & Electronics Shri Vishnu Engineering College for Women Bhimavaram, India alfoni.ee08@gmail.com

ABSTRACT Field Programmable Gate Arrays (FPGAs) are increasingly being used in motor control applications due to their robustness. The PWM signals are generated using Hardware Descriptive Language (HDL). FPGA implementation of Pulse Width modulation (PWM) signals provides an economic solution & fast circuit response . robust

OBJECTIVE The objective of this project is to design a FPGA based controller for BLDC motor which is an experimental model implementation in which SPWM strategy is the proposed control scheme . FPGA based speed controller is designed for closed loop operation of the BLDC motor so that the motor runs much close to the reference speed. Realization is done using FPGA SPARTAN 3A DSP Trainer kit from Xilinx with the help of VHDL programming algorithm.

WORK PLAN Stage 1: OBJECTIVE of the project. Stage 2: Study of Existing Program. Execution of Program in XILINX Software. Design step procedure for the Implementation of Design ISE Flow. Stage 3: Principle of generating PWM waveform using FPGA. State Flow Algorithm using MATLAB and SIMULINK environment. Procedure for Generating the VHDL Code. Integrated Software Environment(ISE)

Stage 4: Simulink Model for generating PWM Pulses using SPWM Technique. HDL code generation for the Simulink model in MATLAB Environment. Stage 5(Present): Verifying HDL code with the Mentor Graphics Model-Sim Simulator. Dumping the Program in the FPGA Chip. Hardware Implementation by using SPARTAN-3A Processor.

INTRODUCTION The voltage is varied by changing the duty-cycle of the base PWM which in turn alters the speed of the Motor. Employing FPGA to realize PWM strategies provides simple & hardware design and better speed control. FPGA implementation has the capability of executing several processes in parallel.

BLOCK DIAGRAM The drive system consists: 1.Three-phase AC supply 2.Three- phase Diode bridge Rectifier 3.Three-phase six switch Inverter 4.Brushless DC Motor 5.Controlled circuits (Xilinx processor and Driver circuit).

HARDWARE IMPLEMENTATION USING FPGA Optimization=Perfection/Effective/Functional

PWM GENERATION USING FPGA

ISE DESIGN FLOW

Steps for ISE Design Flow Step 1:Design Entry –Creating Source Files. Step 2: Synthesis- Compiles the design to transform HDL sources into an architecture-specific design. Step 3: Simulation-Verifying the functionality of the design using a simulation tool at various points during the design flow. Step 4: Constraints Entry- Specifies timing, placement, and other design requirements.

Step 5: Implementation-After synthesis, design implementation is RUN, which converts the logical design into a physical file format that can be downloaded to the selected target device. Step 6:Implementation Analysis- After implementation, the design is analyzed for performance against constraints, device resource utilization, timing performance, and power utilization. Step 7:Implementation Improvement- Based on the analysis design results, changes are made to design sources, process properties, or design constraints and then, rerun synthesis, implementation, or both to achieve design closure. Step 8:Device Configuration and Programming- After generating a programming file, the target device is configured. During configuration, you generate configuration files and download the programming files from a host computer to a Xilinx device.

FLOW-CHART of the HDL CODE Initialization of Libraries Entity Declaration Architectural Declaration Signal Declaration Variable Declaration

Algorithm for Pulse Generation Let xx=Carrier Signal yy=Comparing Value 2. Declaring Capturing Signals a, b , c. Interrupt is given based on Capture Values. Choose the Program Open Loop Closed Loop Comparing the Carrier with the value , yy Pulses are generated.

Algorithm for SPWM Technique Initializing the inputs and the outputs. Inputs- Clock, Frequency and Amplitude Output-Pulses Declaring the array of 256 Sine values. From the Ramp signal, c triangular wave is generated. Compare Sine values with the Triangular wave to generate Pulses. Now set the Frequency and Amplitude of Carrier and Sine.

Simulation Results Using MODEL-SIM Simulator

DOWNLOADING THE PROGRAM

PROCEDURE FOR DOWNLOADING THE PROGRAM

EXPERIMENTAL RESULTS Closed Loop Forward Operation: Closed Loop Reverse Operation:

REFERENCES Dayu Wang, Kaiping Yu and Hong Guo, “Functional design of FPGA in a Brushless DC Motor system based on FPGA and DSP”, IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008. Phan Quoc Dzung, Le Minh Phuong, Pham Quang Vinh,Nguyen Minh Hoang, Tran Cong Binh “New Space Vector Control Approach for Four Switch Three Phase Inverter (FSTPI)” International Conference on Power Electronics and Drive Systems- IEEE PEDS 2009,Thailand Jayaram Bhasker, “ VHDL-Primer”, 3rd Edition, Pearson Prentice Hall,1999 Nalin Kant Mohanty, Ranganath Muthu, “A Novel Implementation of Xilinx FPGA Based Four Switch Three Phase IGBT Inverter Fed Induction Motor Drive Using PWM” European Journal of Scientific Research- EuroJournals Publishing, Inc. 2011, Vol.48 No.3 (2011), pp.424-433 Xilinx 12.1 application notes. MATHWORKS –HDL Coder User Guide,R2011a MATLAB R2011a SOFTWARE Environment.

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MATLAB,SIMULINK STATE FLOW ALGORITHM Generating a VHDL Entity Generating VHDL Test Bench Code Verifying Generated Code Prototype=model/design

FLOW CHART OF FPGA DESIGN embedded

GENERATING A VHDL ENTITY Simulation > Configuration Parameters in the Simulink window. Select HDL Code Generation from the list on the left.

GENERATING VHDL TEST BENCH CODE Simulation > Configuration Parameters in the Simulink window. Configuration Parameters > HDL Code Generation > Test Bench > Generate Test Bench

Sinusoidal PWM Technique

Triangular Wave Generator

Generated Six Pulses

VHDL Code Generation in MATLAB Command Window ### Begin VHDL Code Generation 1. Working on PWM/Subsystem/PS-Simulink Converter/EVAL_KEY as hdlsrc\EVAL_KEY.vhd 2.Working on PWM/Subsystem/PS-Simulink Converter as hdlsrc\PS_Simulink_Converter.vhd 3.Working on PWM/Subsystem/Simulink-PS Converter/EVAL_KEY as hdlsrc\EVAL_KEY_block.vhd 4.Working on PWM/Subsystem/Simulink-PS Converter as hdlsrc\Simulink_PS_Converter.vhd 5.Working on PWM/Subsystem/Solver Configuration/EVAL_KEY as hdlsrc\EVAL_KEY_block1.vhd 6.Working on PWM/Subsystem/Solver Configuration as hdlsrc\Solver_Configuration.vhd 7.Working on PWM/Subsystem as hdlsrc\Subsystem.vhd 8.Working on PWM as hdlsrc\PWM.vhd 9.Working on PWM/powergui as hdlsrc\powergui.vhd 10.Generating package file hdlsrc\PWM_pkg.vhd ### HDL Code Generation Complete.

VERIFYING GENERATED CODE The previously generated code and test bench are taken to HDL simulator for simulation execution and verification of results. Simulated and Verified Generated HDL Code is observed with the Mentor Graphics ModelSim simulator.