CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY1 A Digital Trigger for CTA Cameras K.-H. Sulanke DESY

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY2 Introduction trigger based on a single, low cost FPGA processes 49 pixels regions (center cluster + 6 surrounding) regions overlap by one cluster –the trigger board is plugged to the clusters backplane –FPGA internal clock rate of about 400 MHz (2.5 ns) Interface spec. by Riccardo Paoletti and colleagues

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY3 49 Pixel Trigger Regions clusters of a MST shown the trigger region overlaps by one cluster always 7 cluster trigger region

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY4 The FPGA‘s Functionality delay 49 pixel trigger fabric fanout progr. delays PLL Altera CYCLONE III (or IV E) trigger[3..0] pix_[0][6..0] pix_[1][6..0] pix_[6][6..0] clock from center cluster from surrounding clusters to surrounding clusters pix*_[0][6..0] calibrate STM trig_in_[5..0] trig_out_[5..0] to central trigger board to surrounding clusters (optional) FPGA

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY5 Various Interfaces, To Be Defined Mechanical –Board size, mounting hole positions,..., incl. tolerances –Connector types / positions / orientations Electrical –Power supplies (e.g. +/- 3.3V), max. current, max. ripple –Connector signals –Signal type / level (e.g. differential, LVDS level) –Clock frequency, signal timing Software –API (application programming interface)

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY6 Dig. Trigger, Interface Specifications Mechanical –7 pixel, heaxagonal shape, 52.8 mm grid (50 mm now  ) –Mounting hole positions compatible to RP backplane –Connector types Electrical –3.3V Power supply, max. current ?, 1 A assumed –DAQ board connector signals defined by Riccardo Paoletti –L0 trigger inputs and trigger outputs are LVDS –LVDS Clock, 100 MHz (or similar, <250 MHz, drives PLL) Software –To be defined if needed

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY7 Performance and Simulation Performance FPGA design dependent, checked recently: –Asynchronous mode: E.g. 3NN (better 3 connected) of 49 pixel with minmum overlap of 1ns –Synchronous mode: Algorithm see above, 400 Mhz (2.5ns) Individual L0 signal delay adjustment (calibration cycle) –With current Altera-FPGA design: in steps of 0.8ns, simulated –After migrating to Xilinx: in steps of 50 ps Realistic timing simulation (by Serguei Vorobiov) –VHDL testbench, Modelsim, stimuli from trigsim (finally)

CTA Trigger and Integration Meeting, HU Berlin, Implementation of realistic digital trigger simulations CTA Trigger and Integration Meeting Humboldt University, Berlin 7 November 2011 Goal : detailed digital trigger efficiency check for various trigger patterns First stage input : simulated digital waveforms, final stage input: discriminators' output from trigsim FPGA simulation using ModelSim-Altera (Serguei Vorobiov), Synthesis & Implementation using Quartus Created testbench (in VHDL language), based on the time model of the Cyclone IV FPGA Shown : 3nn trigger patterns simulation on a 7 pixel cluster

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY9 Trigger / Readout Interface The Digital Trigger board will be controlled by the DAQ board: –FPGA (trigger algorithm) update / status monitoring –Calibration on /off (delay adjustment) Trigger clock, provided by a central clock source –E.g. by the Clock distribution system by Axel Kretzschmann clock can be passed through, to the DAQ board Trigger (output) signal can be passed to three destinations: –DAQ board (via backplane) –And / or 6 surrounding neighbor clusters –Central L2 trigger unit with loop back to the DAQ board (via trigger board +backplane)

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY10 The Trigger Board Interfaces FPGA trigger output clock input L0 trigger to / from surrounding clusters Signal connections to / from the center cluster top view bottom view Power from backplane FPGA update by DAQ board

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY11 Timing Management Perfect delay alignment for all 49 pixel is crucial for the digital trigger Auto calibration cycle, FPGA internal, initiated by the DAQ board –needs a central laser diode or a similar light source Time stamping should take place in the DAQ board –All could have a synchronized (by PPS) counter E.g 48+bit, 10+ MHz Buffer for GPS time string + counter snapshot every second (one per camera) Fine timing by analyzing the analog pipeline readout

CTA Trigger and Integration Meeting, HU Berlin, /25/2016K.-H. Sulanke, DESY12 Mechanics compatible to Dragon–Italy and Dragon-Japan DAQ board „Dragon“ Backplane Trigger board HV-board 49 pixel arrangement